Modeler connects RTL, SystemC simulation News & Analysis 5/31/2004 Post a comment Adveda Inc. is introducing this week a model generator simulation add-on that places a SystemC or PLI wrapper around RTL code so Adveda's fast models can be used with established top-down and bottom-up verification environments.
High-level synthesis rollouts enable ESL News & Analysis 5/31/2004 Post a comment Three vendors promise to lift ASIC and FPGA designers above today's RTL design methodologies with high-level synthesis tools they will roll out this week. Mentor Graphics, Celoxica and Bluespec all claim huge productivity gains as well as quality-of-results improvements.
Cadence, CoWare partner on ESL-to-RTL verification News & Analysis 5/31/2004 Post a comment Last September's partnership between CoWare Inc. and Cadence Design Systems Inc. has yielded its first fruits, as the companies are this week introducing a new co-developed flow they claim will allow users of CoWare's ConvergenSC SystemC-based prototyping system to "seamlessly" transfer models built in SystemC and Verilog to Cadence's Incisive verification platform.
Silvaco offers full-chip RC extraction News & Analysis 5/28/2004 Post a comment Offering its first full-chip parasitic extraction product, Silvaco International has released Hipex, which claims "3D accurate" resistance and capacitance (RC) extraction. It's based on the same Digital Equipment Corp. (DEC) technology that was used to build Simplex extraction products, according to Silvaco.
Improving timing closure with physical synthesis News & Analysis 5/28/2004 Post a comment Physical synthesis tools need an overhaul, says Cadence Design Systems' Ashutosh Mauskar (right). He details new requirements for improving timing closure, including wire topology modeling, capacity, and global optimization.
Cadence eröffnet F&E-Center in Moskau News & Analysis 5/28/2004 Post a comment Im Rahmen seiner Globalisierungsstrategie hat Cadence Design Systems ein Büro in Moskau eröffnet. Der Anbieter von EDA-Software setzt damit seine strategischen Investitionen in Russland fort. Die neue Einrichtung ist gleichzeitig das erste EDA-Forschungs- und Entwicklungszentrum, das in Russland von einem ausländischen Unternehmen betrieben wird.
Verilog schism feared as Accellera bypasses IEEE 1364 News & Analysis 5/27/2004 Post a comment Setting the stage for what critics fear could result in a Verilog language schism, the Accellera standards organization voted Thursday (May 27) to donate SystemVerilog 3.1a to a new IEEE working group. Bypassing the IEEE 1364 committee will result in a faster standard, said Dennis Brophy, Accellera chair (right).
TransEDA releases new code coverage tools News & Analysis 5/27/2004 Post a comment Adding to its portfolio of verification tools, TransEDA has released a new tool for specification coverage and impact analysis, as well as a new "coverability analysis" option to its VN-Cover code coverage tool.
ASIC-Style Design Techniques for Programmable Devices Design How-To 5/26/2004 Post a comment Advances in process technology are enabling an increase in the number of applications for FPGAs. FPGA gate counts have increased and prices have fallen, whereas ASIC costs per gate continue to climb. In this feature article, Hier Design's Salil Raje explains how an ASIC-style methodology alleviates problems faced by FPGAs increased complexity.
EDA Tools Bolster Chip Recovery Design How-To 5/26/2004 Post a comment While there are several reasons why the IC industry is coming out of its worst recession in history, one that stands out is EDA support for both design tools and design methodology. During the economic downturn, EDA vendors devoted large amounts of time and money to helping chip vendors operate more effectively when their business picked up. That time has arrived. In this commentary, Jim Lipman examines the new DFM integrated tool suites.
Synopsys adds testbench features to VCS News & Analysis 5/25/2004 Post a comment Evolving its VCS Verilog simulator into a more complete verification environment, Synopsys is announcing a new VCS release with added testbench capabilities. It includes features derived from Synopsys' Vera products.
Prolific offers tool to assure signal integrity News & Analysis 5/24/2004 Post a comment Library-generation tool vendor Prolific Inc. is announcing that the latest version of ProTiming, its timing optimizer, works with Synopsys Inc.'s PrimeTime SI static tool and can automatically repair signal integrity problems in the IC implementation tool flow.
Free software download helps speed A/D converter design Product News 5/24/2004 Post a comment Analog Devices today announced the launch of
its ADIsimADC(TM) software design tool that allows systems designers
to simulate analog-to-digital converter (ADC) performance, speeding
the evaluation and design process. The software is available as a free
download from the ADI website.
Testbench integrated on emulator News & Analysis 5/24/2004 Post a comment Verisity Ltd. continues to integrate the hardware-based verification products acquired with Axis Systems Inc. into its own testbench generation tool to create system-on-chip design solutions.
Startup offers new 'route' to IC design News & Analysis 5/24/2004 Post a comment Armed with a new tool that provides IC routing, extraction, and signal integrity, startup Silicon Design Systems is ready to compete with established providers of IC implementation tools, says Naeem Zafar (right), CEO.
EDA's MRE to Fuel the Semiconductor Industry Design How-To 5/24/2004 Post a comment Meals Ready to Eat (MREs) are modern marvels of food science engineering. But MREs might never have been developed if not for Spam. Its packaging was sealed to keep out contaminants, yet Spam was designed with its own key to allow controlled access to the "food product" inside. Spam was, quite literally, the first turnkey meal. In this commentary, Vin Ratford of Giga Scale IC describes the first turnkey EDA tool for the semiconductor industry, which gets the job done when it comes to chip design
Aptix gets new CEO following Mohsen jailing News & Analysis 5/22/2004 Post a comment Taking charge of a small EDA company that filed for bankruptcy protection after its former CEO was jailed, Hamdi El-Sissi has become the new CEO of Aptix Corp. El-Sissi has not worked in EDA but has held various executive positions in the semiconductor industry.
Formal approach eases multiple clock design News & Analysis 5/21/2004 Post a comment Multiple, independent clocks can cause a variety of problems. Authors from Real Intent, including Jay Littlefield (right), review five challenges posed by multiple clocks, and outline a formal "clock intent verification" methodology that can avoid them.
Synopsys cites low growth, but eyes 'retooling' News & Analysis 5/19/2004 Post a comment Synopsys Inc. only reported one percent year-to-year revenue growth for its fiscal second quarter ending April 30, 2004. But the company beat Wall Street expectations, and views the quarter as evidence that the EDA industry is on the road to recovery as customers "retool."
Magma will bei strukturierten ASICs und FPGAs mitmischen News & Analysis 5/19/2004 Post a comment Magma Design Automation, ein bisher auf Implementierungstools für ASICS spezielisierter Softwareanbieter, will mit neuen Tools seiner Blast-Produktreihe auch in den Märkten für FPGAs und strukturierten ASICs Fuß fassen. Die Produkte sollen noch in dieser Woche vorgestellt werden.
IEEE extends VHDL synthesis subset News & Analysis 5/18/2004 Post a comment Offering a significant extension of the VHDL RTL synthesis subset, the IEEE has approved a revised standard, IEEE 1076.6-2004. The revision will expose the "synthesizable power" of VHDL, said J. Bhasker, chair of the IEEE 1076.6 VHDL synthesis interoperability working group.
Cadence accelerates routing with 'super-threading' News & Analysis 5/18/2004 Post a comment Claiming speedups of 12-16 fold for 20 CPUs, Cadence Design Systems Tuesday (May 18) announced a "super-threading" capability for its NanoRoute IC router. The new capability lets users run NanoRoute over a distributed computing network.
Tool analyzes power across IC, package News & Analysis 5/17/2004 Post a comment XcitePI, a power integrity analysis tool from Sigrity Inc., simulates full-chip power grids and distributed wave propagation effects on an IC's package plane to examine power integrity issues occurring between ICs and packages.
Neue Branchengruppe will SystemVerilog fördern News & Analysis 5/17/2004 Post a comment SANTA CRUZ Mit vereinten Kräften will eine Gruppe von EDA-Anbietern erreichen, dass sich ihre Tools in herstellerübergreifenden Produktionsabläufen einsetzen lassen. Dazu muss der SystemVerilog-Code portabler und wettbewerbsfähiger werden. Im einzelnen will die Gruppe bei Entwicklung, Tests und Assertion-Subsets für SystemVerilog zusammenarbeiten.
Design-specific standard cells yield custom performance News & Analysis 5/14/2004 Post a comment Restricting yourself to one standard cell library can limit performance. In this article Debashis Bhattacharya (right), Zenasis founder and CTO, describes ways of creating design-specific standard cells, ranging from simple cell substitution to on-the-fly creation.
EDA vendor, Accellera moves place SystemVerilog at crossroads News & Analysis 5/14/2004 Post a comment The SystemVerilog language has reached a turning point as a coalition of EDA vendors calls for a phased implementation of the standard. Meanwhile, EE Times has learned, the Accellera standards organization may be reconsidering its donation of SystemVerilog to the IEEE 1364 committee.
Neuer Cadence-Kapitän kommt von Intel News & Analysis 5/14/2004 Post a comment Cadence Systems, einer der größte Anbieter von Software für das Chipdesign, hat einen Praktiker als neuen CEO und President ausgewählt: Michael Fister, der bisher in Intels Enterprise Platforms Group Prozessoren entwickelte, wird künftig die Geschicke des Unternehmens leiten. Der bisherige Cadence-Chef Ray Bingham wechselt in den Aufsichtsrat.
0-In tool verifies metastability effects News & Analysis 5/13/2004 Post a comment Claiming a "breakthrough" solution for the automatic verification of metastability effects, 0-In Design Automation is preparing Archer CDC-FX, an addition to its clock-domain crossing (CDC) verification tool. It claims to verify all possible clock-domain crossing metastability effects.
Synopsys erweitert DesignWare-Library um CoolFlux-DSP News & Analysis 5/13/2004 Post a comment Synopsys-Anwender können im Rahmen künftig Philips' neuen DSP-Core 'Coolflux' in ihre Designs einbeziehen. Eine entsprechende Übereinkunft haben die beiden Unternehmen im Rahmen von Synopsys' Programm 'DesignWare Star IP' abgeschlossen. Über 25 000 Designer können von dem Abkommen profitieren.
Sequence teams with startup for power grid design News & Analysis 5/12/2004 Post a comment Bringing power grid design into its analysis and optimization flow, Sequence Design is announcing a partnership with startup Golden Gate Technology. Sequence will integrate technology from Golden Gate's GoPower product into its PowerTheater RTL analysis tool and its CoolTime and PhysicalStudio analysis and optimization products.
Intel exec replaces Bingham as Cadence CEO News & Analysis 5/12/2004 Post a comment Reaching into industry for new leadership, Cadence Design Systems Wednesday (May 12) announced that former Intel executive Michael Fister has been named president and CEO. He replaces Ray Bingham, who has been elected chairman of Cadence's board of directors.
Package can be integration platform News & Analysis 5/10/2004 Post a comment Over the past few years the electronics industry has been forced to look at different approaches to system integration, addressing the urgent need to develop systems that enable cost reduction and decreasing time-to-market windows
SiPs form good SoC alternative, but designer beware News & Analysis 5/10/2004 Post a comment Before the system-on-chip there was the multichip module. This technology, which bonded dice to a silicon or laminate substrate within a single package, still thrives in high-value applications that demand dense integration of diverse technologies, such as the microwave and military markets.
3-D ICs address SiPs' technical shortfalls News & Analysis 5/10/2004 Post a comment As the multiple-dice vs. single-die battle rages on, the alternative of three-dimensional IC technology has matured to the point where multiple memory, logic or processor dice, each designed in their optimal process technologies, can be combined to form a single multilevel die using a covalent bonding technique.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.