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Content tagged with Design Tools (EDA)
posted in May 2005
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Technology said to speed SoC time-to-market by six months
Product News  
5/31/2005   Post a comment
FPGA-based electronic system level design provider S2C has introduced new interconnect technology designed to enable system-on-chip design using plug-and-play intellectual property modules.
Sigrity tools focus on IR drop analysis for packages and boards
News & Analysis  
5/31/2005   Post a comment
Sigrity introduced two standalone tools customized for analysis of voltage drop on packages and printed circuit boards.
Synopsys claims enhanced tool can speed verification by up to 5X
News & Analysis  
5/31/2005   Post a comment
Synopsys said new capabilities added to its VCS register-transfer level product can improve verification speed by up to five times.
Built-in self-test migrates to register-transfer level
Product News  
5/31/2005   Post a comment
Built-in self-test offers high fault coverage for a range of potential defects, but it has been difficult to implement. LogicVision promises to change that this week with its LV2005 release, moving logic and memory BIST insertion up to the register-transfer level.
Data path tools do the math for area savings
Product News  
5/31/2005   Post a comment
New mathematical approaches that promise up to 40 percent savings in silicon area will become available to a broader audience this week, as intellectual-property startup Arithmatica rolls out its first EDA tools.
First wave of IP support washes over FPGA family
Product News  
5/31/2005   Post a comment
Lattice Semiconductor Corp. has released for its recently announced LatticeXP field-programmable gate array (FPGA) family the first set of IP modules that address the needs of the consumer, computing and communications markets.
Tool brings power analysis to virtual-prototyping phase
Product News  
5/31/2005   Post a comment
Bringing power analysis into the IC virtual-prototyping phase, Silicon Dimensions this week will announce the latest version of Chip2Nite, a design-planning tool aimed at logic designers.
VPM-T allows modifications to a virtual processor model ISA
Product News  
5/31/2005   Post a comment
VaST Systems today (May 31, 2005) released its new Virtual Processor Model Transformer (VPM-T) for use by early adopters, enabling modification of the instruction set of a seed processor model.
Virtual system prototypes speed multiprocessor design
Design How-To  
5/30/2005   Post a comment
Graham Hellestrand, emeritus professor and CTO of Vast Systems Technology, discusses the design challenges of multiprocessor "supersystems" and shows how virtual system prototypes can speed system development.
Averant releases updated Solidify property verification tool
Product News  
5/27/2005   Post a comment
Register transfer level (RTL) verification provider Averant released the latest version of its Solidify property verification tool, Solidify 3.1.
French EDA startup to demo netlist reduction tools at DAC
News & Analysis  
5/27/2005   Post a comment
French EDA startup EdXact plans to introduce two versions of its standalone netlist reduction tool, Jivaro, at next month's Design Automation Conference.
Mentor vor Übernahme von Aptix
News & Analysis  
5/27/2005   Post a comment
Ein Jahr nachdem der Radid-Prototyping-Anbieter Aptix Konkurs anmelden musste, schickt sich der EDA-Software-Anbieter Mentor Graphics an, die Reste des Technologieunternehmens aufzukaufen.
Verification tool adds SystemVerilog support
Product News  
5/26/2005   Post a comment
Verification tool provider VeriEZ Solutions Inc. will off SystemVerilog support for its EZVerify product, the company said. SystemVerilog support will be available to beta customers in the fourth quarter.
Verification tool provider to demo new system-level tools at DAC
News & Analysis  
5/26/2005   Post a comment
Aldec said it would stage private demonstrations of its new generation of system-level design capabilities and features during next month's Design Automation Conference.
Ansoft reports 49% increase in fourth quarter earnings
News & Analysis  
5/26/2005   Post a comment
EDA tool provider Ansoft reported fiscal fourth quarter net income of $4.7 million, up 49 percent from the $2.8 million, or 21 cents per diluted share, that the company reported for the year-ago quarter.
Aprio to demo design-side DFM technology at DAC
News & Analysis  
5/26/2005   Post a comment
Aprio Technologies plans to demonstrate its design-side technology, built around incremental optical proximity correction, at next month's Design Automation Conference.
Mentor acquires automotive network design tool provider
News & Analysis  
5/26/2005   Post a comment
Mentor Graphics has acquired Swedish automotive networking and data communication solutions provider Volcano Communications Technologies for undisclosed considerations.
Simulation software sets power designs in motion
Product News  
5/26/2005   Post a comment
International Rectifier's new web-based simulation tool for three-phase, variable-speed, motor drive inverter circuits simplifies recursive calculations and expands the design support for the company's iMOTION integrated design platform.
Profits, revenue up at Wind River
News & Analysis  
5/25/2005   Post a comment
Wind River Systems reported a GAAP net income of $1.9 million for the first fiscal quarter of 2006, a considerable improvement from the net loss of $3.8 million reported for the year-ago quarter.
Jasper releases new version of flagship verification product
News & Analysis  
5/25/2005   Post a comment
Jasper Design Automation has released a new version of the company's flagship formal verification product, JasperGold 4.0, as well as a "push button" version of JasperGold for assertion-based verification, JasperGold Express.
EDA vendors announce flows for IBM-Chartered 90 nm process
News & Analysis  
5/25/2005   Post a comment
IBM and Chartered Semiconductor Manufacturing added common design support to their jointly developed 90 nanometer process platform.
Cadence extends IR drop capability in VoltageStorm
News & Analysis  
5/25/2005   Post a comment
Cadence Design Systems said an improved capability for its VoltageStorm power analysis tool will help engineers determine where to place power rail de-coupling capacitors.
LSI Logic eliminates mask charges for entry-level platform ASICs
Product News  
5/24/2005   Post a comment
LSI Logic is offering two new slices on its RapidChip Integrator2 platform that are designed to provide a low cost option for high-volume applications.
OCP-IP adds two Chinese organizations to membership
News & Analysis  
5/24/2005   Post a comment
Intellectual property plug-and-play standards organization Open Core Protocol International Partnership has added two new Chinese organizations to its membership roster.
ESL advocacy group conducting online survey
News & Analysis  
5/24/2005   Post a comment
ESL Now, a loose organization of more than 20 companies, is inviting users to participate in an online survey regarding current and planned electronic system level tool usage.
Startup adds former Applied president Maydan to board
News & Analysis  
5/24/2005   Post a comment
Former Applied Materials president Dan Maydan (shown) was added to the board of directors of design-for-manufacturability startup Ponte Solutions Tuesday.
Electronics Workbench updates PCB design products
News & Analysis  
5/24/2005   Post a comment
EDA vendor Electronics Workbench Corp. has released the final two components in its Electronics Workbench Series 8 design suite.
Wind River expanding Linux solutions
News & Analysis  
5/23/2005   Post a comment
In a flurry of activity timed to coincide with the company's users conference, device software optimization provider Wind River announced several new products, strategies and alliances.
Power reduction software works with existing design flows
Product News  
5/23/2005   Post a comment
Golden Gate Technology offers power reduction software that works with existing design flows at the architectural and physical levels. The company says it can reduce total power consumption by up to 25%.
Latest Xilinx FPGA design tool aims to boost performance
Product News  
5/23/2005   Post a comment
Xilinx the next generation of the company's field-programmable gate array design and analysis tool, PlanAhead 7.1
Celoxica says new ESL tool is faster, more physical
Product News  
5/23/2005   Post a comment
Celoxica released the fourth generation of its DK Design Suite, DK4, which the company said contains major enhancements and "resets the bar" for C-synthesis performance.
New Denali IP intended for DDR, flash and SATA subsystems
News & Analysis  
5/23/2005   Post a comment
Denali Software introduced a data-subsystem intellectual property product for DRAM, flash memory and hard disk drive interfaces.
Formal approach offers verification 'salvation'
Design How-To  
5/23/2005   Post a comment
Verification guru Harry Foster shows how a prove-as-you-go methodology, coupled with the "mature" use of assertion-based verification, can help rescue users from "verification hell."
New circuit simulation engine for application integrations
Product News  
5/20/2005   Post a comment
Circuit simulation and semiconductor IP characterization software provider Legend Design Technology Inc. has released an application program interface for its MSIM circuit simulator.
Optimal claims first adjacent structure coupling capability
News & Analysis  
5/20/2005   Post a comment
Claiming an industry first, Optimal Corp. has introduced a full-wave adjacent structure coupling capability in the company's Full-Wave Signal Integrity/Power Integrity (SI/PI) simulation flow.
Xoomsys simulation speedup technology moves closer to beta sites
News & Analysis  
5/20/2005   Post a comment
Anjaneya Thakar (shown), president and CEO of startup Xoomsys, says his company's distributed process technology can speed simulation by orders of magnitude.
« Les innovations devraient faire baisser le coût par fonction au-delà de la loi de Moore »
Blog  
5/20/2005   Post a comment
Le coût par fonction des puces devrait continuer de baisser longtemps après que la loi de Moore sera devenue obsolète, grâce aux conceptions futures et à diverses innovations de fabrication, a déclaré Walden Rhines, Président-directeur général de Mentor Graphics Corp.
Popular RF/microwave design suite gets new modules
Product News  
5/20/2005   Post a comment
Eagleware-Elanix's GENESYS 2005 features major new simulation, synthesis, and user interface enhancements as well as frequency planner, mixer synthesis and amplifier synthesis modules.
Software services firm offering DFM/DFY toolkit
News & Analysis  
5/20/2005   Post a comment
EDA software development services company SoftJin has introduced a building block product for design for manufacturing and design for yield tool development
Synplicity extends stock repurchase program
News & Analysis  
5/19/2005   Post a comment
Synplicity's board of directors has extended the company's stock repurchase program, authorizing the repurchase of up to 1 million shares of its common stock over the next year.
New open source initiative seeks to push SystemC adoption
News & Analysis  
5/19/2005   Post a comment
A new open source initiative has been established to provide a mechanism for the sharing and standardization of SystemC intelluctual property.
Design for Manufacturing is Everyone's Business
Design How-To  
5/19/2005   Post a comment
To be a viable volume-production item, a chip must exhibit sufficient yield throughout the manufacturing chain, including fabrication, packaging and test. Just as chip designers must design their products such that they can be successfully tested, they must also take into consideration factors that will maximize the chip's yield after all the relevant manufacturing operations. In this feature article, Jim Lipman discusses design for manufacturing (DFM).
Court rules on Magma's request to dismiss claims by Synopsys
News & Analysis  
5/19/2005   Post a comment
The U.S. District Court issued a ruling on Magma Design Automation's motion to dismiss certain claims brought by Synopsys in the ongoing patent litigation between the two companies.
Synopsys' quarterly loss beats internal targets; CFO moving on
News & Analysis  
5/18/2005   Post a comment
Synopsys reported a GAAP net loss of $4.9 million, or 3 cents per share, for its fiscal second quarter. The company also announced that its CFO is resigning to pursue another opportunity.
Startup claims tools can reduce IC power consumption by 25%
News & Analysis  
5/18/2005   Post a comment
Power reduction has become the No. 1 design concern, according to Golden Gate Technology CEO Dennis Heller, who said his company's new software products can reduce IC power consumption by up to 25 percent.
Cyclone II FPGAs score a trio of development kits
Product News  
5/18/2005   Post a comment
Altera Corp. has rolled out three development kits for its Cyclone II family of low-cost, second-generation FPGAs. The three kits cover the Nios II processor family, DSP, and PCI designs.
ispLEVER-starter design tools enhanced to support entire FPGA line
Product News  
5/18/2005   Post a comment
Lattice Semiconductor Corp. has upgraded its ispLEVER-Starter 5.0 design tools and is offering it free of charge to promote evaluation of its recently announced ispLEVER 5.0 programmable logic design tool suite.
Updated RF design tool suite promotes ease of use
News & Analysis  
5/18/2005   Post a comment
Eagleware-Elanix has released an upgrade to its Genesys RF and microwave design suite.
Neue Simulations-Funktionen für SystemVerilog
Product News  
5/18/2005   Post a comment
Mit Mentor Graphics und Axiom Design Automation bringen diese Woche gleich zwei Anbieter von Verifizierungssoftware eine neue Simulationstechnologie, die den aufkommenden Sprachstandard SystemVerilog unterstützt.
Rhines: Innovations will decrease cost-per-function post-Moore's Law
News & Analysis  
5/17/2005   Post a comment
Moore's Law isn't a law at all, according to Mentor Graphics CEO Walden Rhines (pictured), who says other innovations will decrease IC cost-per-function after its fall.
Page 1 / 2   >   >>


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