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Content tagged with Design Tools (EDA)
posted in May 2005
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Japan's VLSI Design and Education Center joins OCP-IP
News & Analysis  
5/17/2005   Post a comment
Japan's VLSI Design and Education Center has joined the intellectual property plug-and-play standards organization Open Core Protocol International Partnership.
Zuken upgrades PCB design suite
News & Analysis  
5/17/2005   Post a comment
Zuken announced a major upgrade to its CR-5000 enterprise-wide printed circuit board (PCB) design suite of tools. The upgrade includes 44 productivity enhancements in schematic capture, PCB layout and simulation, the company said.
Celoxica introduces new pilot board for teaching and evaluation
Product News  
5/17/2005   Post a comment
Celoxica has introduced the RC10 Pilot board, a high-density, field-programmable gate array-based embedded system teaching and evaluation platform built specifically for designers, teachers and students who want to pilot C-based design and synthesis.
Philips-CTO fordert bessere EDA-Tools
Product News  
5/17/2005   Post a comment
Um den Integrationsgrad im Chipgeschäft zu erhöhen, muss die Industrie zunächst einmal das Thema 'System in Package' (SiP) lösen. Und dafür benötigt die Branche nicht nur umfassendere EDA-Tools, sondern auch bessere Standards. Das ist jedenfalls die Auffassung von Rene Penning de Vires, Chief Technology Officer von Philips Semiconductors.
IP startup secures $6 million in VC funding
News & Analysis  
5/16/2005   Post a comment
IPextreme, a startup focused on providing on-chip intellectual property subsystems, has secured $6 million in Series A funding from venture capital firms Alloy Ventures and SmartForest Ventures.
Cadence names six new corporate VPs
News & Analysis  
5/16/2005   Post a comment
Cadence Design Systems Inc. Monday announced six high-level appointments.
How FPGA packaging drives signal integrity
News & Analysis  
5/16/2005   Post a comment
Good package design is critical for good noise performance in FPGAs, says Xilinx' Panch Chandrasekaran. This article shows how package design considerations impact system performance.
Tenison EDA seeks to speed ESL adoption
News & Analysis  
5/13/2005   Post a comment
Tenison EDA CEO Martin Harding (pictured), says the industry needs to bridge the "model gap" to facilitate the widepread adoption of electronic system level design.
Mentor achieves certification of USB OTG controller IP
News & Analysis  
5/13/2005   Post a comment
Mentor Graphics said its high-speed universal serial bus (USB) on-the-go (OTG) controller has achieved USB OTG certification from the USB Implementers Forum.
Sarnoff introduces design products for ESD optimization
News & Analysis  
5/13/2005   Post a comment
Sarnoff Europe has introduced two new products for electrostatic discharge optimization in fabless chip design, the TakeCharge design kit and the ESDdoctor.
New open modular architectural control standard available
News & Analysis  
5/13/2005   Post a comment
The Open Modular Architecture Controls Users' Group (OMAC) has released the PackSoft application library, a technical paper describing a new standard designed to give users more transparency in machine programming, debugging and maintenance.
Startup says new product will revolutionize routing
News & Analysis  
5/12/2005   Post a comment
Two-year-old EDA startup Silicon Design Systems introduced its first product, an IC router that the company says will revolutionize routing the way that physical synthesis did placement.
Synopsys IP achieves USB OTG certification
News & Analysis  
5/12/2005   Post a comment
Synopsys' DesignWare universal serial bus on-the-go digital core and three physical interfaces intellectual property have been certified by the USB Implementers Forum.
Denali adds USB support to PureSpec verification IP
News & Analysis  
5/12/2005   Post a comment
Denali's PureSpec verification intellectual property is now available for the verification of USB designs, including USB 2.0 and USB OTG interfaces.
Altium schnürt seine EDA-Tools zu einem Paket
News & Analysis  
5/12/2005   Post a comment
Der australische EDA-Softwareanbieter Altium will seine gesamte Produktpalette unter einem gemeinsamen Marken-Dach zusammenfassen. Statt einer Vielzahl verschiedener Tools hat es der Kunde künftig mit einem Gesamtpaket zu tun, aus dem er je nach Bedarf unterschiedliche Funktionalitäten lizenzieren kann.
EVE s’allie à Tensilica pour accélérer le développement de systèmes sur puce
News & Analysis  
5/12/2005   Post a comment
Emulation and Verification Engineering (EVE) et Tensilica Inc. ont annoncé la signature d’un accord visant à accélérer la conception de systèmes sur puces (SoC) complexes avec des processeurs Xtensa multiples.
EDA veteran Zafar to lead startup Pyxis Technology
News & Analysis  
5/12/2005   Post a comment
Longtime Quickturn Design Automation executive Naeem Zafar (pictured) chose Pyxis Technology because of a strong team of founders and technology that seeks to bridge physical design and manufacturing.
FishTail joins two Mentor partner programs
News & Analysis  
5/11/2005   Post a comment
FishTail Design Automation Inc. has joined Mentor Graphics Corp.'s OpenDoor and ModelSim Value Added Partnership programs.
Synopsys closes Nassda acquisition
News & Analysis  
5/11/2005   Post a comment
Synopsys Inc. has received clearance from the U.S. Federal Trade Commission and closed its acquisition of Nassda Corp
Former analyst Jordan joins Cadence
News & Analysis  
5/11/2005   Post a comment
Former Wells Fargo Securities analyst Jennifer Jordan was named corporate vice president of investor relations at Cadence Design Systems Inc.
Altera enhances SOPC Builder tool for FPGA designers
Product News  
5/10/2005   Post a comment
Altera has added new capabilities to its SOPC Builder tool to further boost the productivity of field-programmable gate array designers.
Mentor's CheckerWare verification IP supporting OCP interface
News & Analysis  
5/10/2005   Post a comment
Open Core Protocol International Partnership said the OCP interface has been added to Mentor Graphics Corp.'s CheckerWare library of verification intellectual property.
Tensilica, EVE partner to speed SoC development times
News & Analysis  
5/10/2005   Post a comment
Tensilica and Emulation and Verification Engineering have signed an agreement aimed at speeding the design of complex system-on-chips with multiple Xtensa processors.
Synopsys' PCI Express IP solution achieves PCI-SIG compliance
News & Analysis  
5/10/2005   Post a comment
Synopsys said its DesignWare physical layer and digital controller intellectual property have achieved compliance with the PCI Express standard from the PCI-Special Interest Group. According to Synopsys, the combination is the first data link and PHY solution from a single vendor to pass compliance.
Chip-Designtool nimmt Power-Probleme unter die Lupe
Product News  
5/10/2005   Post a comment
Spannungsabfall und Elektromigration in Halbleiterstrukturen will Synopsys mit einer neuen Design-Software in den Griff bekommen. Das EDA-Tool heißt 'PrimeRail' und kombiniert die statische und dynamische IC-Analyse für die Transistor- und Gatter-Ebene.
Jasper's Kranen wins 2005 'women in EDA' award
News & Analysis  
5/9/2005   Post a comment
Kathryn Kranen, president and CEO of Jasper Design Automation, has been named the 2005 Marie R. Pistilli Women in EDA Achievement Award winner. Kranen will be presented the award during the Design Automation Conference Workshop for Women in EDA.
Cadence and Faraday Technology to collaborate on library views
News & Analysis  
5/9/2005   Post a comment
Faraday Technology Corp. has joined Cadence Design Systems Inc.'s OpenChoice intellectual property program. The two companies intend to co-develop a list of library views to facilitate digital implementation and signal integrity under United Microelectronics Corp.'s 130-nanometer Fusion process.
A guide to better EMC for pc-board design
Design How-To  
5/9/2005   Post a comment
Zuken's John Berrie shows how basic frequency-domain concepts can help you achieve better electromagnetic compatibility (EMC) with printed circuit board design.
Bei 90 Nanometer ist vieles neu - aber dennoch vertraut
Blog  
5/9/2005   Post a comment
In Regionen unterhalb von 100 Nanometer wird für Chipdesigner alles anders... oder vielleicht doch nicht? Unser Gastbeitrag zeigt, welchen neuen Herausforderungen sich der Entwickler gegenübersieht – und welche vertrauten Probleme ihn weiterhin begleiten.
Accellera exploring open compression standard
News & Analysis  
5/6/2005   Post a comment
EDA standards organization Accellera has created an open compression technical coordinating committee to explore the development of an open compression standard for non-proprietary on-chip test data compression structures.
Synopsys releases deposition transcripts, Magma follows suit
News & Analysis  
5/6/2005   Post a comment
In a battle of spin control, both Synopsys and Magma have published slightly different versions of transcripts of the recent deposition of the central figure in their high-profile patent dispute.
Si2 to host open library modeling meeting at DAC
News & Analysis  
5/5/2005   Post a comment
The Silicon Integration Initiative will present the results of a year-long technical study of critical issues in characterization and modeling in IC libraries at an open meeting during the Design Automation Conference.
Magma co-founder wants deposition transcript unsealed
News & Analysis  
5/5/2005   Post a comment
Saying that Synopsys treated facts selectively in a declaration that he signed, Lukas van Ginneken wants the court to unseal a recent deposition he gave lawyers from both companies.
Nassda, Synopsys still waiting on FTC
News & Analysis  
5/4/2005   Post a comment
After five months of waiting, it appears the EDA industry will be waiting at least one more week for Synopsys Inc.'s proposed acquisition of Nassda Corp.
FishTail granted patent for technology underlying products
News & Analysis  
5/4/2005   Post a comment
The automated timing constraint technology underlying FishTail Design Automation's products has been granted a patent by the U.S. Patent Office.
DSP brings serial RapidIO and 2MBytes to infrastructure video, telecom and imaging apps
Product News  
5/4/2005   Post a comment
Taking aim at network and video infrastructure end-equipments and high-end imaging systems, Texas Instruments has launched its TMS320C6455 digital signal processor touting reduced code size plus more on-chip memory and high bandwidth integrated peripherals including the Serial RapidIO bus for interprocessor communications. The TMS320C6455 DSP will come in 1 GHz, 850 MHz and 720 MHz versions.
Xilinx introduces new design tools for its DSPs
Product News  
5/4/2005   Post a comment
Xilinx Inc. has introduced new design tools aimed at easing the implementation of high sample rate or multi-channel signal processing designs onto Xilinx DSP devices.
Atrenta expands RTL analysis and verification
News & Analysis  
5/4/2005   Post a comment
Claiming new capabilities for IC design, Atrenta Inc. rolled out "predictive development" tools for RTL analysis and assertion-based verification Wednesday.
Magma buys back convertible notes
News & Analysis  
5/4/2005   Post a comment
Magma Design Automation said it repurchased through private transactions convertible notes valued at $44.5 million for about $35 million, reducing its number of dilluted shares outstanding by 1.9 million.
EDA startup names three new executives to European team
News & Analysis  
5/3/2005   Post a comment
Pulsic Limited, a provider of physical design tools for complex IC designs, announced three executive appointments.
Cadence formal analysis claims ease of use
News & Analysis  
5/2/2005   Post a comment
Cadence Design Systems this week is introducing Incisive Formal Verifier, a tool that aims to make it easy for IC designers verify assertions in RTL code.
First product from new firm selling Japanese EDA tools in U.S.
News & Analysis  
5/2/2005   Post a comment
A new company founded to bring EDA technology from Japan to customers in the U.S. has announced the availability of its first product, a GDSII and photomask viewer developed by Dai Nippon Printing.
QuickLogic introduces programmable controller for Intel PXA2XX processor line
News & Analysis  
5/2/2005   Post a comment
QuickLogic Corp. has introduced a programmable controller optimized for the Intel PXA2XX processor line based on Intel Corp.'s XScale technology.
Agilent, CST enhance integration for RF and MW circuit design
News & Analysis  
5/2/2005   Post a comment
Agilent Technologies Inc. and Computer Simulation Technology (CST) have made two major advances in the integration of CST's Microwave Studio simulation tool with Agilent's Advanced Design System (ADS) software).
Cadence formal analysis claims ease of use
News & Analysis  
5/2/2005   Post a comment
Cadence Design Systems this week is introducing Incisive Formal Verifier, a tool that aims to make it easy for IC designers verify assertions in RTL code.
The 'why' and 'what' of algorithmic synthesis
Design How-To  
5/2/2005   Post a comment
What is algorithmic synthesis, how does it differ from "behavioral" synthesis, and how does it work? Mentor Graphics' Bryan Bowyer answers those questions in this article.
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