Synopsys, Zuken tie simulation to boards News & Analysis 5/30/2007 Post a comment Promising an integrated platform for system-level design, simulation, and verification, Synopsys and Zuken will link Synopsys' Saber simulator to Zuken's CR-5000 pc-board design environment.
Synopsys, ARM define low-power methodology News & Analysis 5/29/2007 Post a comment Authors from Synopsys and ARM have joined forces to write a Low Power Methodology Manual in order to define a common methodology for such techniques as multi-voltage design, power gating, and voltage scaling.
Edxact demo's enhanced netlist reduction tools at DAC Product News 5/29/2007 Post a comment Edxact SA, a French EDA startup company specializing in parametric extraction and physical verification, announced it would demonstrate new versions of its Jivaro netlist reduction technology and Comanche interconnection analysis tool at the Design Automation Conference early June in San Diego, California.
Achieving Certified IP Quality Efficiently Design How-To 5/29/2007 Post a comment The increasing use of design IP has reduced design effort per gate for the chip designer, but it has had an inverse effect on the chip-level integration and functional verification effort. This article explains how using complete formal functional verification enables IP providers to certify highest IP quality, and to do so cost-effectively and with a high productivity.
Sierra fuels 45 nm IC physical design Product News 5/28/2007 Post a comment Offering new support for 45 nm IC design, Sierra Design Automation is upgrading its Olympus-SoC design suite with a new global routing solution, a multi-corner clock tree synthesis capability, and a 45 nm "ready" router.
Power integrity suite spans ICs, packages, boards Product News 5/28/2007 Post a comment Promising a comprehensive noise and power analysis solution for chip, package and pc-board design, Apache Design Solutions is announcing Sentinel, a product line that generates compact Spice-compatible models for portability across design teams.
Forte claims SystemC-to-GDSII flow Product News 5/25/2007 Post a comment Forte Design Systems is claiming an automated path from SystemC to GDSII with Cynthesizer 3.3, a new release of its behavioral synthesis tool that links to Magma Design Automation's Blast Create.
In the Eye of the DFM/DFY Storm Design How-To 5/25/2007 Post a comment A very important point that is often overlooked is that the "D" in both "DFM" and "DFY" stands for "Design." On this basis, post-processing the GDSII files to correct problems introduced by the upstream design tools cannot truly be considered to be DFM/DFY.
PDF buys silicon IP startup Fabbrix News & Analysis 5/24/2007 Post a comment PDF Solutions has purchased startup Fabbrix Inc., a provider of silicon intellectual property that promises a lithography-friendly alternative to conventional standard cell design.
Partnership links FPGA, board design News & Analysis 5/23/2007 Post a comment An alliance between Zuken and Aldec promises to help FPGA and pc-board designers work more closely together, and keep track of changing FPGA pin assignments as boards are developed.
Measuring Scan Compression Performance Design How-To 5/21/2007 Post a comment Scan compression reduces the amount of data needed for digital IC manufacturing tests, thereby lowering the cost of executing patterns on the tester. In this article, we focus on three fundamental performance metrics: fault coverage loss, pattern inflation, and area overhead.
Magma updates DRC, adds yield analysis Product News 5/21/2007 Post a comment Magma Design Automation is upgrading its design rule checking (DRC) and layout-versus-schematic (LVS) capabilities, and rolling out a new Quartz Yield analysis tool in cooperation with PDF Solutions.
Timing Constraints Generation Technology Design How-To 5/17/2007 Post a comment Properly created timing constraints, as suggested in this paper from Atrenta, not only reduce the total effort to achieve timing closure, but also reduce the number of iterations to achieve that goal.
Cadence updates custom IC, PCB design News & Analysis 5/15/2007 Post a comment Cadence Design Systems is claiming significant upgrades to its custom IC design and pc-board design solutions, including a "complete" custom IC simulation and verification solution.
Signal Integrity Analysis in Wireless SoCs Design How-To 5/14/2007 Post a comment Huge digital IPs, such as microprocessors, digital signal processors, or encryption engines, are being assembled together with analog blocks " e.g. power supply control, data conversion " and radio-frequency (RF) " LNA, VCOs, Mixers. The former, aka the aggressor, generates lots of interfering noise, which gets disseminated through the entire system to finally degrade the operation of the most sensitive circuitry (the victim). Coupling Wave Solutions presents one method for successful design of
Cadence 'kit' eases low-power IC design Product News 5/14/2007 Post a comment Cadence Design Systems is announcing a Low-Power Methodology kit with a representative design, intellectual property (IP), and scripts to help users implement low power design techniques.
Accellera approves SCE-MI 2.0 to speed acceleration News & Analysis 5/11/2007 Post a comment The Accellera standards organization announced Friday (May 11) its approval of the Standard Co-Emulation Modeling Interface (SCE-MI) version 2.0, an enhanced specification that links transaction-level models to hardware acceleration and emulation.
Viewpoint: Automotive Electronics Benefits from System in Package Designs Design How-To 5/11/2007 Post a comment The Design Automation Conference's Automotive theme couldn't come at a better time as new system-in-package (SiP) control devices offer unmatched capabilities to support high-speed, high-definition image processing and smart sensors. With widespread use of SiP comes the concern that they are often over designed and unable to fit their package. All too often, a hardware engineer will rely on a spreadsheet to determine optimization and trade-off decisions and not an automated solution.
Commentary: ANSI C won't work for ESL Design How-To 5/10/2007 Post a comment ANSI C and C++ are fundamentally unsuited for hardware design, leaving SystemC as the best choice for electronic system level (ESL) design tools and flows, says Forte Design's Mike Meredith.
Verifying Configurable Verification Interfaces Using OCP Design How-To 5/10/2007 Post a comment The Open Core Protocol (OCP) is a synchronous socket interface specification that is widely used in the semiconductor industry today for System-on-Chip (SoC) designs. Verifying protocol interfaces is a challenging exercise for any verification group. Formal verification of protocols has become far more prevalent in recent years because of its ability to exhaustively remove all doubt of incorrect interface behavior prior to tape-out.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.