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Content tagged with Design Tools (EDA)
posted in May 2007
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Commentary: Let's change the dialogue between engineers, managers
News & Analysis  
5/31/2007   Post a comment
It's no secret that demands on engineers have gotten tougher. Moore's Law and design complexity continue their inexorable climb.
Averant claims advances in formal verification
Product News  
5/31/2007   Post a comment
Averant Inc. is claiming several technology advancements in formal verification with the release of Solidify 5.0, the latest version of its formal property verification tool.
Goering spots 'what's hot' at DAC '07
News & Analysis  
5/31/2007   Post a comment
Software and design editor Richard Goering is gearing up for the 2007 Design Automation Conference in San Diego with a "what's hot" list.
Xilinx simplifies memory interface designs with complete FPGA solutions
Product News  
5/30/2007   Post a comment
Built-in features, easy-to-use software, free reference designs, and development kits enable users to quickly implement FPGA-based memory interfaces with good design margins.
Synopsys, Zuken tie simulation to boards
News & Analysis  
5/30/2007   Post a comment
Promising an integrated platform for system-level design, simulation, and verification, Synopsys and Zuken will link Synopsys' Saber simulator to Zuken's CR-5000 pc-board design environment.
Synopsys, ARM define low-power methodology
News & Analysis  
5/29/2007   Post a comment
Authors from Synopsys and ARM have joined forces to write a Low Power Methodology Manual in order to define a common methodology for such techniques as multi-voltage design, power gating, and voltage scaling.
Edxact demo's enhanced netlist reduction tools at DAC
Product News  
5/29/2007   Post a comment
Edxact SA, a French EDA startup company specializing in parametric extraction and physical verification, announced it would demonstrate new versions of its Jivaro netlist reduction technology and Comanche interconnection analysis tool at the Design Automation Conference early June in San Diego, California.
Cadence attacks assertion-based verification bottlenecks
Product News  
5/29/2007   Post a comment
Cadence Design Systems has updated its functional verification tools with three new capabilities that claim to relieve bottlenecks in assertion-based verification.
Achieving Certified IP Quality Efficiently
Design How-To  
5/29/2007   Post a comment
The increasing use of design IP has reduced design effort per gate for the chip designer, but it has had an inverse effect on the chip-level integration and functional verification effort. This article explains how using complete formal functional verification enables IP providers to certify highest IP quality, and to do so cost-effectively and with a high productivity.
Brion targets designers with lithography tool
Product News  
5/28/2007   Post a comment
Brion Technologies' first product aimed at IC design teams, Tachyon Lithography Aware Design (LAD), helps designers discover and correct lithography-induced hot spots before tapeout.
Sierra fuels 45 nm IC physical design
Product News  
5/28/2007   Post a comment
Offering new support for 45 nm IC design, Sierra Design Automation is upgrading its Olympus-SoC design suite with a new global routing solution, a multi-corner clock tree synthesis capability, and a 45 nm "ready" router.
Power integrity suite spans ICs, packages, boards
Product News  
5/28/2007   Post a comment
Promising a comprehensive noise and power analysis solution for chip, package and pc-board design, Apache Design Solutions is announcing Sentinel, a product line that generates compact Spice-compatible models for portability across design teams.
CoFluent presents new architecture exploration facility
Product News  
5/25/2007   Post a comment
French Electronic System Level (ESL) company CoFluent Design announced it would demonstrate version 2.1 of CoFluent Studio, a functional and architectural design tool, at the Design Automation Conference early June in San Diego, California.
Forte claims SystemC-to-GDSII flow
Product News  
5/25/2007   Post a comment
Forte Design Systems is claiming an automated path from SystemC to GDSII with Cynthesizer 3.3, a new release of its behavioral synthesis tool that links to Magma Design Automation's Blast Create.
In the Eye of the DFM/DFY Storm
Design How-To  
5/25/2007   Post a comment
A very important point that is often overlooked is that the "D" in both "DFM" and "DFY" stands for "Design." On this basis, post-processing the GDSII files to correct problems introduced by the upstream design tools cannot truly be considered to be DFM/DFY.
Synplicity speeds FPGA-based prototype debugging
Product News  
5/24/2007   Post a comment
Synplicity Inc. has introduced Identify Pro, a software solution that promises to provide full debugging visibility into FPGA-based hardware prototypes for ASIC and ASSP verification.
Cooley survey: SystemVerilog up, SystemC down
News & Analysis  
5/24/2007   Post a comment
A verification survey conducted by John Cooley concludes at SystemC usage has fallen below expectations of two years ago, and SystemVerilog usage is up, but it's for verification rather than design.
PDF buys silicon IP startup Fabbrix
News & Analysis  
5/24/2007   Post a comment
PDF Solutions has purchased startup Fabbrix Inc., a provider of silicon intellectual property that promises a lithography-friendly alternative to conventional standard cell design.
Viewpoint: With ESL and Emulation, Who Needs Simulation?
Design How-To  
5/24/2007   Post a comment
ESL synthesis and emulation can combine to provide an efficient verification and validation platform, especially for software developers.
Routing experts launch 'interconnect synthesis' startup
News & Analysis  
5/24/2007   Post a comment
IC routing experts who designed key products for Avanti Corp. have launched Nanovata Design Automation, a company that will use shape-based technology to optimize IC layouts.
How to simplify hardware prototyping with EXP modules
Design How-To  
5/23/2007   Post a comment
New EXP specification defines a versatile expansion interface to FPGA baseboards that offers designers flexibility, performance, and ease of use during hardware development.
Partnership links FPGA, board design
News & Analysis  
5/23/2007   Post a comment
An alliance between Zuken and Aldec promises to help FPGA and pc-board designers work more closely together, and keep track of changing FPGA pin assignments as boards are developed.
10-GbE switch management tool accelerates system development
Product News  
5/23/2007   Post a comment
The ControlPoint software suite from Fulcrum enables equipment providers to rapidly deliver high-performance networking and embedded switch systems with advanced functions based on its FocalPoint family of switch chips.
Characterization supports 45 nm memories
News & Analysis  
5/23/2007   Post a comment
Legend Design Technology has upgraded its CharFlo-Memory tool suite to support memory characterization challenges at 45 nm and below.
Multicore systems require architectural optimization
Blog  
5/22/2007   Post a comment
I expect that those DAC attendees focused in the present will want to talk about DFM and Power, while those looking into the needs for the next few years will want to debate multicore issues.
Measuring Scan Compression Performance
Design How-To  
5/21/2007   Post a comment
Scan compression reduces the amount of data needed for digital IC manufacturing tests, thereby lowering the cost of executing patterns on the tester. In this article, we focus on three fundamental performance metrics: fault coverage loss, pattern inflation, and area overhead.
Magma updates DRC, adds yield analysis
Product News  
5/21/2007   Post a comment
Magma Design Automation is upgrading its design rule checking (DRC) and layout-versus-schematic (LVS) capabilities, and rolling out a new Quartz Yield analysis tool in cooperation with PDF Solutions.
Register description format gets 'Spirit' of standardization
Product News  
5/21/2007   Post a comment
Denali Software has donated SystemRDL, the register description language used in its Blueprint product, to the Spirit Consortium for development into a standard specification format.
Axiom DA buys Indian verification company
News & Analysis  
5/18/2007   Post a comment
Badru Agarwala, CEO of Axiom Design Automation, says his company's purchase of Bangalore firm SysChip Design Technologies will add protocol coverage checking to Axiom's IC verification tools.
Commentary: New hope for analog layout automation
News & Analysis  
5/17/2007   1 comment
Automation is sorely lacking for analog physical design, but new technology and an open infrastructure are providing new hope, says Jim Solomon, Cadence Design Systems founder.
ESL provider launches register management tool
Product News  
5/17/2007   Post a comment
Duolog Technologies, an Irish provider of electronic system level (ESL) services and tools, is announcing the commercial availability of BitWise, a tool that generates register and memory map information.
Timing Constraints Generation Technology
Design How-To  
5/17/2007   Post a comment
Properly created timing constraints, as suggested in this paper from Atrenta, not only reduce the total effort to achieve timing closure, but also reduce the number of iterations to achieve that goal.
CriticalBlue Announces Multicore Methodology for Single Threaded Software
Product News  
5/17/2007   Post a comment
CriticalBlue has announced that it has added multicore development capability to its Cascade coprocessor synthesis solution.
'OnDemand' models speed firmware debugging
Product News  
5/16/2007   Post a comment
Carbon Design Systems is rolling out new technology that can automatically disable cycle-accurate software models when they're inactive, thus speeding firmware debugging.
Cadence updates custom IC, PCB design
News & Analysis  
5/15/2007   Post a comment
Cadence Design Systems is claiming significant upgrades to its custom IC design and pc-board design solutions, including a "complete" custom IC simulation and verification solution.
Cadence Introduces Complete Custom IC Simulation and Verification Solution
Product News  
5/15/2007   Post a comment
The new release of Cadence's Virtuoso Multi-Mode Simulation Solution Enables Fast and Accurate Verification of Designs Across Analog, RF, Custom Digital, Memory and Mixed-Signal Domains.
Signal Integrity Analysis in Wireless SoCs
Design How-To  
5/14/2007   Post a comment
Huge digital IPs, such as microprocessors, digital signal processors, or encryption engines, are being assembled together with analog blocks " e.g. power supply control, data conversion " and radio-frequency (RF) " LNA, VCOs, Mixers. The former, aka the aggressor, generates lots of interfering noise, which gets disseminated through the entire system to finally degrade the operation of the most sensitive circuitry (the victim). Coupling Wave Solutions presents one method for successful design of
Cadence buys U.C. Berkeley DFM spinoff
News & Analysis  
5/14/2007   Post a comment
Cadence Design Systems has purchased CommandCAD, a design for manufacturability (DFM) startup launched by graduate students from the University of California at Berkeley.
Cadence 'kit' eases low-power IC design
Product News  
5/14/2007   Post a comment
Cadence Design Systems is announcing a Low-Power Methodology kit with a representative design, intellectual property (IP), and scripts to help users implement low power design techniques.
Accellera approves SCE-MI 2.0 to speed acceleration
News & Analysis  
5/11/2007   Post a comment
The Accellera standards organization announced Friday (May 11) its approval of the Standard Co-Emulation Modeling Interface (SCE-MI) version 2.0, an enhanced specification that links transaction-level models to hardware acceleration and emulation.
Viewpoint: Automotive Electronics Benefits from System in Package Designs
Design How-To  
5/11/2007   Post a comment
The Design Automation Conference's Automotive theme couldn't come at a better time as new system-in-package (SiP) control devices offer unmatched capabilities to support high-speed, high-definition image processing and smart sensors. With widespread use of SiP comes the concern that they are often over designed and unable to fit their package. All too often, a hardware engineer will rely on a spreadsheet to determine optimization and trade-off decisions and not an automated solution.
HW/SW co-design becomes an essential chore
News & Analysis  
5/11/2007   Post a comment
Hardware-software co-design has emerged as a key first step in future design projects, engineering managers agree.
System provides pre-RTL performance analysis
Product News  
5/10/2007   Post a comment
Chip Estimate has developed technology that enables performance analysis at the earliest phase of the chip design cycle.
Control register templates speed address maps
Product News  
5/10/2007   Post a comment
Semifore, an EDA startup that generates IC address maps, is announcing a partnership that will provide control register templates for its users.
Commentary: ANSI C won't work for ESL
Design How-To  
5/10/2007   Post a comment
ANSI C and C++ are fundamentally unsuited for hardware design, leaving SystemC as the best choice for electronic system level (ESL) design tools and flows, says Forte Design's Mike Meredith.
Verifying Configurable Verification Interfaces Using OCP
Design How-To  
5/10/2007   Post a comment
The Open Core Protocol (OCP) is a synchronous socket interface specification that is widely used in the semiconductor industry today for System-on-Chip (SoC) designs. Verifying protocol interfaces is a challenging exercise for any verification group. Formal verification of protocols has become far more prevalent in recent years because of its ability to exhaustively remove all doubt of incorrect interface behavior prior to tape-out.
Tool boosts PCB design automation
Product News  
5/10/2007   Post a comment
Design automation software provider DesignAdvance Systems has launched CircuitSpace 2.1, a design automation tool for PCB component placement.
Zuken ups high-speed PCB design support
Product News  
5/9/2007   Post a comment
Zuken has updated its flagship CR-5000 pc-board design environment with support for high-speed technologies and devices including DDR memory and high-speed FPGAs.
Mentor announces synthesis support for Altera's new Arria GX FPGA family
Product News  
5/8/2007   Post a comment
Altera and Mentor have been in close cooperation to ensure Precision Synthesis support for the full range of low-cost, transceiver-based Arria GX FPGA devices.
Static checker completes SystemVerilog support
Product News  
5/8/2007   Post a comment
The EZVerify static analysis tool from VeriEZ Solutions now addresses the complete SystemVerilog language, including design, assertions and testbenches, according to the company.
Page 1 / 2   >   >>


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