Gray Code Fundamentals – Part 1 Design How-To 5/28/2011 5 comments The term Gray code is typically used to refer to a binary sequence in which only a single bit changes value when transitioning between adjacent states.
Mentor, Magma top expectations News & Analysis 5/27/2011 1 comment Mentor Graphics CEO Walden Rhines said Mentor's board has met once by phone since three members nominated by billionaire financier Carl Icahn were elected to join it.
Zombie tales for people with brains Blog 5/26/2011 7 comments When I come to think about it, I’ve actually been seeing quite a lot of these little rascals recently, starting with The Walking Dead television series followed by all sorts of books…
Got Discworld? Blog 5/25/2011 23 comments I am a HUGE fan of the author Terry Pratchett in general and of his Discworld books in particular. If you've not been exposed to these little rascals you are missing a real treat...
IMEC and the ARM connection Blog 5/25/2011 6 comments European research institute IMEC is holding its annual technology forum. It has one of those slides with more than a hundred partner logos and ARM's was nowhere to be seen. So what was ARM CEO Warren East doing at the event?
Measuring return on investment of model-based design Design How-To 5/25/2011 Post a comment Model-Based Design for embedded software development lowers costs by identifying defects early in the development process and reducing the total number of latent defects. By helping companies deliver higher-quality systems at lower cost and in less time, Model-Based Design provides a competitive advantage.
IMEC, Atrenta to show 3-D design flow at DAC Product News 5/24/2011 3 comments EDA company Atrenta Inc., working with the IMEC research institute on a 3-D integration project, has developed a planning and partitioning design flow for heterogeneous 3-D stacked IC assemblies. They plan to demo the flow at the DAC exhibition.
VMM based multi-layer framework for system level verification Design How-To 5/23/2011 Post a comment
This article describes the traditional method used in system-level verification and how the new approach improves it, explaining the layered architecture with an overview of the advantages it presents. Techniques to improve runtime with proper threading and memory management are described, as well as methods to overcome issues of large compilation time using separate compilation and multi-core compilation techniques.
NI to buy EDA vendor and RF design firm News & Analysis 5/23/2011 6 comments National Instruments Inc. has signed a definitive agreement to acquire AWR Corp. a supplier of EDA software for designing high-frequency components and systems. The purchase price of $58 million includes $7 million in cash on the AWR balance sheet, NI said.
Book Review: Idea Man by Paul Allen Engineer’s Bookshelf 5/22/2011 2 comments Idea Man is billed as “A Memoir by the Cofounder of Microsoft” – and this is actually a really good way of presenting a book that’s sort-of, but not quite, an autobiography.
Open source protocol targets 'Internet of things' Product News 5/22/2011 Post a comment NXP Semiconductors has announced it will make the IEEE 802.15.4 based wireless connectivity network layer software it inherited from the acquisition of Jennic, JenNET-IP, open source, in a bid to generate greater interest in the 'Internet of Things' concept.
Time to exploit IDEs for hardware design and verification Design How-To 5/18/2011 7 comments By taking a closer look at the differences between the general software and the more specialized hardware verification communities, this article will attempt to explain the current growth and future prospects of IDEs in hardware verification. The implications for hardware design are also examined.
Blog Doing Math in FPGAs Tom Burke 2 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...