Architectural power cuts News & Analysis 6/13/2001 Post a comment Germany-based Offis Systems & Consulting has developed a power estimation tool that can be used at the architectural level to find the lowest-power design for an algorithm.
Synplicity's entry in ASIC synthesis focuses on design gap problem News & Analysis 6/5/2001 Post a comment SUNNYVALE, Calif. -- Synplicity Inc. here figures it is doing something rather unusual with its entry into the ASIC synthesis market. Instead of focusing strictly on leading-edge designs, the company is emphasizing productivity and mainstream ASICs, which are produced with 0.35- to 0.18-micron processes.
Replay available now: A handful of emerging network technologies are competing to be the preferred wide-area connection for the Internet of Things. All claim lower costs and power use than cellular but none have wide deployment yet. Listen in as proponents of leading contenders make their case to be the metro or national IoT network of the future. Rick Merritt, EE Times Silicon Valley Bureau Chief, moderators this discussion. Join in and ask his guests questions.