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posted in June 2002
Après DAC—But Wait, There's More
Design How-To  
6/18/2002   Post a comment
The Design Automation Conference is over, but some additional product announcements promise exciting design advancements down the road. TechOnLine's Jim Lipman discusses some of the ones that were of particular interest to him.
Complete SoC Design, Verification Reign at DAC Exhibits
Design How-To  
6/7/2002   Post a comment
So you're going to the Design Automation Conference and don't know where to start on the exhibit floor? Save your shoe leather—TechOnLine's Jim Lipman takes you on a DAC virtual tour of some the most interesting products in several key technology areas.
Static crosstalk analysis assures silicon success
Design How-To  
6/5/2002   Post a comment
With the rapid move to ultradeep submicron designs and feature size processes of 0.13 micron and below, ensuring the integrity of signals as they traverse conductors on a chip is becoming a challenge.
Signal integrity permeates design process
Design How-To  
6/5/2002   Post a comment
Designers agree that they must address signal integrity when using a 0.13-micron process or below. But less clear is just how and where in the design flow signal integrity should be dealt with.
Signal integrity drives post-layout verification
Design How-To  
6/5/2002   Post a comment
Accelerant Networks is a developer of high-integration ICs that allow rapid development of intelligent, high-speed backplane connection systems.
IC layout must avoid crosstalk problems
Design How-To  
6/5/2002   Post a comment
With process technologies evolving from 0.18 micron to 0.13 micron and on to 90 nanometers, signal integrity effects are strongly influencing the performance of integrated circuits.
How crosstalk causes problems
Design How-To  
6/5/2002   Post a comment
Signal integrity effects are becoming ever more visible for geometries of 0.13 micron and below.
Early power estimates guide IP selection
Design How-To  
6/5/2002   Post a comment
Aura Communications is a fabless semiconductor company that has developed an enabling technology for low-cost, low-power, wireless personal-area networks.
Deep submicron design is more than just 'noise'
News & Analysis  
6/5/2002   Post a comment
Designers have brought designs as low as 0.18 micron to tapeout without signal integrity closure, although at the expense of performance.
Crosstalk, power haunt UDSM designs
News & Analysis  
6/5/2002   Post a comment
A clear understanding of design-integrity issues and the ability to control related problems are prerequisites for first-time success in silicon.
ALF facilitates SI-aware design flow
News & Analysis  
6/5/2002   Post a comment
Many of the challenges facing EDA tool users graduating to ASIC-style system-on-chip (SoC) design at 0.13 micron and below can be addressed through the use of new methodologies taking advantage of the Advanced Library Format (ALF).
Physical Design Flow Taps Partition Layout
News & Analysis  
6/4/2002   Post a comment
Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its...
Language Attributes Ensure IC Verification
News & Analysis  
6/4/2002   Post a comment
Hardware verification languages (HVLs) have survived past the critical early-adopter stage and are now aggressively entering the mainstream.
FPGA Designs Take on Timing Closures
News & Analysis  
6/4/2002   Post a comment
Over the last couple of years, FPGAs have made amazing advances in performance and capacity. Solutions, such as physical synthesis, are now needed that allow designers to take advantage of these improvements.
Rosetta Blooms for System-level Design
News & Analysis  
6/4/2002   Post a comment
The EDA industry has made significant progress in developing system-level design tools and languages for functional verification.
Comms SOC Design Challenges Tool Capability
News & Analysis  
6/4/2002   Post a comment
Continuing advances in process technology give us the ability, in principle, to design ever-more-complex communications systems-on-chip at higher speeds.
System C: a realistic SoC debug strategy
News & Analysis  
6/3/2002   Post a comment
As Moore's Law steams ahead, the resulting rush to retool for ever-smaller geometries has led to the realization by most leading companies designing systems-on-chip that the emphasis in SoCs is on that "S," for system.
Adapting traditional embedded debug strategies to SoC designs
News & Analysis  
6/3/2002   Post a comment
Embedded systems are becoming more complex. The trend in silicon design has been to put the whole system on a single chip.


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