Techniques to make clock switching glitch free News & Analysis 6/26/2003 1 comment Clock switching can cause glitches, but there are ways to avoid them. Rafey Mahmud, applications engineer at Altera, presents two methods for avoiding glitches at output clock lines in this tutorial article.
Using "Empty Space" for IC Congestion Relief News & Analysis 6/26/2003 Post a comment In past technologies, the ratio between device size and minimum wire width
and spacing was large enough to reserve enough routing resources, so the
fixed-die approach yielded nearly 100% utilization. However, in today's deep
submicron technologies, shrinking device size no longer reserves enough wire
tracks to complete the routing. Hence, wire area has become a major factor in
completing a design. It is not uncommon that more than half of the modern chip
is occupied by "white space" or "in
Jury Still Out for EDA Industry on Structured ASICs News & Analysis 6/25/2003 Post a comment Structured ASICs are generating an enormous buzz in the silicon design world,
promising lower mask and tool costs, faster time-to-market and performance
comparable to standard-cell ASICs with the design simplicity of FPGAs. But it
remains to be seen whether the new business will prove to be the next big avenue
of growth or a dead end for electronic design automation.
EDA Quality Remains Elusive Goal News & Analysis 6/25/2003 Post a comment Like jumbo shrimp and military intelligence, the term "EDA quality" is an oxymoron for most working
engineers. Electronic design automation companies are forever trying to catch up
with Moore's Law by writing quality code to address the complex nuances of chip
design. But for many tool makers today, the quality summit remains as elusive a
goal as Mount Everest's peak once was for climbers.b
"Toned-Down" DAC Holds Few Surprises Design How-To 6/20/2003 Post a comment The annual electronics design-tool Mecca known as the Design Automation Conference (DAC) took place the first week in June, accompanied by the collective finger crossing of EDA tool vendors and customers alike. Jim Lipman reviews the most important developments of the show.
Maximize CPU power for physical verification Design How-To 6/13/2003 Post a comment At 130 nm, physical verification jobs consume gigabytes of memory. In this article, Cadence Design Foundry engineer Colin Stewart shows you how to make best use of machines, operating systems, hierarchy, multi-threading, and the Load Sharing Facility (LSF).
Programmable Analog Parts Make a Tough Filter Design Easy News & Analysis 6/9/2003 Post a comment Filters have always presented some of the toughest challenges in analog design: the math is difficult, the circuit selection is based on a variety of subtle criteria, and the component tolerances are critical. Tradeoffs between the variables are time-consuming and not always well defined.
DAC 2003: Emphasis on Accuracy News & Analysis 6/9/2003 Post a comment After several years of relentless emphasis on reducing time to market the spotlight at the 40th Design Automation Conference (DAC) in Anaheim shifted noticeably away from accelerating the design process and toward design performance and accuracy. In other words doing it right, especially the first time, is gaining favor over doing it quickly.
An Overview of SystemVerilog 3.1 News & Analysis 6/6/2003 Post a comment SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along with a rich set of new features for verifying model functionality. The author presents an overview of the features in the SystemVerilog 3.1 standard.
Does asynchronous logic design really have a future? Design How-To 6/6/2003 Post a comment The synchronous vs. asynchronous design debate erupts every now and then, usually when a vocal minority swears by asynchronous design, often claiming that asynchronous design delivers higher performance, lower power, or both, mostly with arguments and without any supporting evidence.
Clockless IC designs are ready to compete Design How-To 6/6/2003 Post a comment When semiconductor companies cite chip performance levels, the immediate follow-up question is increasingly, "But at what power consumption?" The performance/power efficiency debate is picking up as today's systems-from the data center to the shirt pocket-must be power efficient to either save on batteries, cut heat output or conserve electricity.
'Complexity Crisis' Roils EDA, Analyst Says News & Analysis 6/2/2003 Post a comment The 100 million gate complexity made possible by 90 nanometer processes caused "panic" among power EDA users last year, and will fuel the demand for electronic system level (ESL) tools, according to Gary Smith, chief EDA analyst at Gartner Dataquest. Smith spoke at Dataquest's Sunday (June 1) briefing at the Design Automation Conference in Anaheim.