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Content tagged with Design Tools (EDA)
posted in June 2003
Techniques to make clock switching glitch free
News & Analysis  
6/26/2003   1 comment
Clock switching can cause glitches, but there are ways to avoid them. Rafey Mahmud, applications engineer at Altera, presents two methods for avoiding glitches at output clock lines in this tutorial article.
Using "Empty Space" for IC Congestion Relief
News & Analysis  
6/26/2003   Post a comment
In past technologies, the ratio between device size and minimum wire width and spacing was large enough to reserve enough routing resources, so the fixed-die approach yielded nearly 100% utilization. However, in today's deep submicron technologies, shrinking device size no longer reserves enough wire tracks to complete the routing. Hence, wire area has become a major factor in completing a design. It is not uncommon that more than half of the modern chip is occupied by "white space" or "in
Jury Still Out for EDA Industry on Structured ASICs
News & Analysis  
6/25/2003   Post a comment
Structured ASICs are generating an enormous buzz in the silicon design world, promising lower mask and tool costs, faster time-to-market and performance comparable to standard-cell ASICs with the design simplicity of FPGAs. But it remains to be seen whether the new business will prove to be the next big avenue of growth or a dead end for electronic design automation.
EDA Quality Remains Elusive Goal
News & Analysis  
6/25/2003   Post a comment
Like jumbo shrimp and military intelligence, the term "EDA quality" is an oxymoron for most working engineers. Electronic design automation companies are forever trying to catch up with Moore's Law by writing quality code to address the complex nuances of chip design. But for many tool makers today, the quality summit remains as elusive a goal as Mount Everest's peak once was for climbers.b
"Toned-Down" DAC Holds Few Surprises
Design How-To  
6/20/2003   Post a comment
The annual electronics design-tool Mecca known as the Design Automation Conference (DAC) took place the first week in June, accompanied by the collective finger crossing of EDA tool vendors and customers alike. Jim Lipman reviews the most important developments of the show.
Using 'empty space' for IC congestion relief
Design How-To  
6/19/2003   Post a comment
Up to half of a chip's die size may be "empty space." Tsu-Wei Ku, president and founder of Apex Designs, shows how you can propagate empty space to alleviate congestion and reduce die size.
Maximize CPU power for physical verification
Design How-To  
6/13/2003   Post a comment
At 130 nm, physical verification jobs consume gigabytes of memory. In this article, Cadence Design Foundry engineer Colin Stewart shows you how to make best use of machines, operating systems, hierarchy, multi-threading, and the Load Sharing Facility (LSF).
Low-Power Design Techniques Span RTL-to-GDSII Flow
News & Analysis  
6/12/2003   Post a comment
In a tutorial Magma Design Automation's Sameer Patel shows how you can minimize static and dynamic power dissipation, voltage drop and electomigration.
A Midyear Look at EDA
News & Analysis  
6/11/2003   Post a comment
Despite the general doom and gloom, the EDA industry is alive and well, says Wally Rhines,
Programmable Analog Parts Make a Tough Filter Design Easy
News & Analysis  
6/9/2003   Post a comment
Filters have always presented some of the toughest challenges in analog design: the math is difficult, the circuit selection is based on a variety of subtle criteria, and the component tolerances are critical. Tradeoffs between the variables are time-consuming and not always well defined.
DAC 2003: Emphasis on Accuracy
News & Analysis  
6/9/2003   Post a comment
After several years of relentless emphasis on reducing time to market the spotlight at the 40th Design Automation Conference (DAC) in Anaheim shifted noticeably away from accelerating the design process and toward design performance and accuracy. In other words doing it right, especially the first time, is gaining favor over doing it quickly.
Low-power design techniques span RTL-to-GDSII flow
Design How-To  
6/9/2003   1 comment
Magma Design Automation's Sameer Patel presents techniques you can use to minimize dynamic and static power dissipation, voltage drop, and electromigration in this tutorial article.
An Overview of SystemVerilog 3.1
News & Analysis  
6/6/2003   Post a comment
SystemVerilog is an extensive set of enhancements to the IEEE 1364 Verilog-2001 standard. These enhancements provide powerful new capabilities for modeling hardware at the RTL and system level, along with a rich set of new features for verifying model functionality. The author presents an overview of the features in the SystemVerilog 3.1 standard.
Does asynchronous logic design really have a future?
Design How-To  
6/6/2003   Post a comment
The synchronous vs. asynchronous design debate erupts every now and then, usually when a vocal minority swears by asynchronous design, often claiming that asynchronous design delivers higher performance, lower power, or both, mostly with arguments and without any supporting evidence.
Clock domain modeling is essential in high density SoC design
News & Analysis  
6/6/2003   Post a comment
Whether designing SOCs with traditional synchronous logic or alternative locally, or self-clocked "asynchronous" blocks, verification has become more important, difficult and time consuming, particularly if there are multiple clock domains to consider.
Breaking the EDA barrier in async design
Design How-To  
6/6/2003   Post a comment
With individual chips approaching 50-million-gate equivalents and inception to delivery time measured in months, efficient design automation flows have become mandatory enabling technology.
Time to dispel clockless logic design myths
News & Analysis  
6/6/2003   Post a comment
ASIC designs are presenting design challenges that are increasing the stress on engineering design teams.
Clockless IC designs are ready to compete
Design How-To  
6/6/2003   Post a comment
When semiconductor companies cite chip performance levels, the immediate follow-up question is increasingly, "But at what power consumption?" The performance/power efficiency debate is picking up as today's systems-from the data center to the shirt pocket-must be power efficient to either save on batteries, cut heat output or conserve electricity.
'Complexity Crisis' Roils EDA, Analyst Says
News & Analysis  
6/2/2003   Post a comment
The 100 million gate complexity made possible by 90 nanometer processes caused "panic" among power EDA users last year, and will fuel the demand for electronic system level (ESL) tools, according to Gary Smith, chief EDA analyst at Gartner Dataquest. Smith spoke at Dataquest's Sunday (June 1) briefing at the Design Automation Conference in Anaheim.


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