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posted in June 2004
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ReShape raises $12 million as EDA funding soars
News & Analysis  
6/30/2004   Post a comment
Riding a wave of new venture capital funding for EDA companies, IC physical design provider ReShape Inc. announced Wednesday (June 30) that it has closed a $12 million round of series C funding. ReShape is among nine EDA companies who have collectively received over $87 million in the first six months of 2004.
Carbon, CoWare link RTL to SystemC
News & Analysis  
6/29/2004   Post a comment
Claiming that co-simulation between a SystemC simulator and an event-driven RTL simulator is no longer needed, EDA startup Carbon Design Systems has announced that its DesignPlayer hardware and software validation modeling system works in CoWare's ConvergenSC SystemC simulation environment.
Design Automation Conference draws 10,500
News & Analysis  
6/29/2004   Post a comment
Sounding an optimistic note for the EDA industry, the Design Automation Conference (DAC) announced that this year's event drew 10,500 participants, the highest total attendance level since 2001. But this figure was only slightly above last year's conference, and well below the peak year of 1998, which drew over 21,000.
CoFluent soutenu par EADS et Airbus
News & Analysis  
6/29/2004   Post a comment
CoFluent Design, éditeur de logiciels de CAO électronique, a annoncé mardi (29 juin) la signature d’une convention avec EADS Développement et Airbus Développement. Par ce soutien, la jeune pousse espère accélérer son développement à l’international.
Barcelona swaps IP model for EDA licensing
News & Analysis  
6/28/2004   Post a comment
Barcelona Design Inc., which emerged in the late 1990s with an unconventional plan for tackling the difficult analog design tool market, has altered its strategy and adopted a more traditional EDA licensing model.
Pulsic releases layout tool for analog RF design
News & Analysis  
6/28/2004   Post a comment
Pulsic Ltd. has released a layout tool targeted specifically at analog RF designs and has introduced a new version of its Lyric Physical Design Framework featuring automatic floor plan generation to drive placement tools. Mike Santarini has this report.
Barcelona ditches service provider model
News & Analysis  
6/28/2004   Post a comment
Barcelona Design Inc., which emerged in the late 1990s with an unconventional plan for tackling the difficult analog design tool market, has altered its strategy and adopted a more traditional EDA licensing model. The company will be selling access to its high-speed simulation tools. The changes recognize the shortcomings of the company's initial approach to analog designers, who were believed resistant to adopting new tools. Mike Santarini offers these insights.
ZiLOG Offers In-Circuit Emulator Kit for Z8 Encore! 64K Family of 8-bit Microcontrollers
Product News  
6/28/2004   Post a comment
ZiLOG, Inc. is offering a high-end development tool that emulates its Z8 Encore! 64K series of 8-bit microcontrollers (MCUs).
ESL 'ecosystem' enables power-efficient ASIPs
News & Analysis  
6/28/2004   Post a comment
An entire "ecosystem" is developing for electronic system level (ESL) design, and it enables custom implementations like application-specific instruction processors (ASIPs), says CoWare CTO Karl Van Rompaey.
Hardware, software speed design-for-test
Product News  
6/28/2004   Post a comment
Design-for-test company Teseda is releasing two new hardware and software products. The company claims its new IC test system is the only one in the industry that's priced at under $200/pin.
Approaches to accelerated HW/SW co-verification
Design How-To  
6/25/2004   Post a comment
Accelerating HW/SW co-verification can speed time to market, according to Cadence Design Systems' Ray Turner (right). He compares three methods that can be used with acceleration or emulation, including instruction set simulation, RTL processor models, and bond-out cores.
French emulation firm raises $7.2M
News & Analysis  
6/25/2004   Post a comment
Preparing for a considerable expansion, French verification provider Emulation and Verification Engineering (EVE) has closed a second round of funding totaling $7.2 million.
Kosteneffektives Kabelbaum-Design für die Automobiltechnik
News & Analysis  
6/25/2004   Post a comment
Selbst einfache Mittelklasse-Pkws enthalten heute so viel Elektronik, dass manch einer vorschlagen möchte, große Elektronikfirmen sollten doch ihre eigenen Automarken auf den Markt bringen. Die Komponenten oder Funktionseinheiten dieser Hersteller machen bereits 60 bis 80 Prozent der gesamten Stückliste eines Fahrzeugs aus. Wer weiß, vielleicht leisten sie damit schon den Großteil der Wertschöpfung in der Produktion?
EVE boucle son 2ème tour de table de 7,2 millions de dollars
News & Analysis  
6/25/2004   Post a comment
Emulation and Verification Engineering (EVE), société franco-américaine de CAO spécialisée dans la création de plates-formes avancées de vérification fonctionnelle de circuits intégrés, a annoncé jeudi (24 juin) avoir effectué sa deuxième levée de fonds d’un montant de 7,2 millions de dollars. Cet investissement devrait lui permettre de renforcer ses initiatives de recherche et développement, ses activités de ventes et de support technique et, éventuellement, d’envisager des acquisitions futures
Synopsys investit dans HPL Technologies, spécialiste de la DFM
News & Analysis  
6/25/2004   Post a comment
Après avoir renoncé à son projet d’acquisition de Monolithic System Technology Inc. (MoSys), Synopsys Inc. a annoncé, mercredi 23 juin, avoir pris une participation de 19,9 % dans HPL Technologies Inc., fournisseur d’un logiciel de conception de produits en fonction de leurs compatibilités avec les opérations de fabrication en aval (design-for-manufacturing ou DFM).
Synopsys invests in DFM specialist
News & Analysis  
6/23/2004   Post a comment
SAN JOSE, Calif.--After scrapping plans to acquire Monolithic System Technology Inc. (MoSys), Synopsys Inc. Wednesday (June 23) said that it has taken a 20 percent stake in HPL Technologies Inc., a supplier of design-for-manufacturing (DFM) software.
EVE passe du prototypage à l’émulation
News & Analysis  
6/23/2004   Post a comment
Emulation and Verification Engineering (EVE) a pris son envol avec des systèmes de prototypage de circuits intégrés sur réseaux prédiffusés programmables à un prix abordable. L’entreprise lance son premier émulateur commercial. Avec son nouveau système ZeBu-XL, EVE espère profiter de l’augmentation des budgets de biens d’équipement des entreprises de conception de puces.
IC route startup snags $6.7M, hires former Monterey VP
News & Analysis  
6/22/2004   Post a comment
Startup Silicon Design Systems (SDS), which introduced an IC routing and extraction product in May 2004, announced this week (June 22) that it has received $6.7 million in new venture capital funding. SDS has also appointed Jacob Greidinger, former vice president of technology at Monterey Design Systems, as its vice president of R&D.
Chip-Designkosten erreichen 100 Millionen Dollar
News & Analysis  
6/22/2004   Post a comment
Die Entwicklungskosten für neue Chips steigen in atemberaubendem Tempo. Manche Designs der nächsten Chipgenerationen könnten die Kostenschwelle von 100 Millionen US-Dollar erreichen, fürchtet ein Manager von Texas Instruments.
EVE moves from prototyping to emulation
News & Analysis  
6/22/2004   Post a comment
After getting its start with low-cost FPGA-based IC prototyping systems, Emulation and Verification Engineering (EVE) is introducing its first commercial emulator this week (June 22). With its new ZeBu-XL system, EVE hopes to tap into expanding capital equipment budgets from chip design firms.
Interconnects to rely on EDA tools for long slog to 65 nm
News & Analysis  
6/21/2004   Post a comment
Serious problems with chip-level interconnects have plagued designers for several years.
Trade tips for scaling interconnects
News & Analysis  
6/21/2004   Post a comment
Interconnect process and integration engineers can be consumed by a near-limitless list of minuscule details, but it is resistance, capacitance, reliability, yield and cost that matter.
Rx for crosstalk, voltage drop
News & Analysis  
6/21/2004   Post a comment
As chips evolve, their increasing complexity-in the number of components, in functionality and in terms of larger, higher-performance, smaller-geometry designs-requires the industry to rethink the way interconnects are viewed.
Improving Parasitic Extraction Accuracy at 65 nm
News & Analysis  
6/21/2004   Post a comment
The rapid scaling of IC technology has produced smaller and faster devices, but along with this has come more resistive interconnects and increased coupling capacitance.
Advanced techniques for 65 nm
News & Analysis  
6/21/2004   Post a comment
The move to 65-nanometer process nodes opens up many exciting opportunities for advances in semiconductor manufacturing techniques, such as porous low-k dielectric materials, selective metal capping and direct plating.
Interconnect modeling below 100 nm
News & Analysis  
6/21/2004   Post a comment
The challenges of accurately predicting product performance, signal and power integrity have increased significantly in sub-100-nanometer technologies.
Optical Fiber Communications
News & Analysis  
6/21/2004   Post a comment
Optical Fiber Communications
Indian software prowess fails to translate to EDA
News & Analysis  
6/18/2004   Post a comment
India's software services firms may be high-profile in the world of IT, but they barely register on the EDA radar. Although most of the big suppliers of electronic design automation tools have development centers here, they have no homegrown competition and don't expect to see any for at least another decade because, as one senior executive said, India's software industry seems to have a one-track mind.
Indian software prowess fails to translate to EDA
News & Analysis  
6/17/2004   Post a comment
India's software services firms may be high-profile in the world of IT, but they barely register on the EDA radar.
Power integrity requires global I/O SSO analysis
News & Analysis  
6/16/2004   Post a comment
I/O cell simultaneous switching output (SSO) can be a major cause of chip failure. Authors from Apache Design Systems, including Yu Liu (right), call for a "global" I/O SSO analysis capability that includes the chip, package, and PCB.
Cadence offers PCB design data management
News & Analysis  
6/16/2004   Post a comment
Cadence Design Systems announced Wednesday (June 16) that it is entering the collaborative design and library data management market by introducing its new Allegro Design Workbench software suite. It's built on technology from product lifecycle management (PLM) company MatrixOne.
Static verification needs a parallel approach
News & Analysis  
6/16/2004   Post a comment
Equivalence checking is an essential technology for verifying large chips. But it needs to overcome capacity limits and embrace parallel computing, says Mentor Graphics' Robert Hum.
Techniques for verifying multiprocessor designs
News & Analysis  
6/14/2004   Post a comment
Multiprocessor verification revolves around memory accesses, say authors from Obsidian Software, including Melanie Typaldos (right). This tutorial describes memory sharing modes and shows what kinds of tests need to be generated for each.
So many questions, so little time: Which Spice will suffice?
Design How-To  
6/14/2004   Post a comment
Let's face it; if you use small 'proved out' designs, and never need to answer 'what if' questions, you probably don't need Spice, writes Intusoft's Tim Ghazaleh in this introduction to Spice modeling in the June issue of Planet Analog magazine. But Spice modeling can verify the performance of your favorite part in a new design " even check the effects of PCB manufacturing variations. (At the very least, check out the gorgeous screen shots.)
Court rules Nassda misappropriated Synopsys code
News & Analysis  
6/14/2004   Post a comment
In a severe blow to Nassda Corp., a discovery referee ruled June 11 that Nassda and its founders copied or derived 60,000 lines of code in its HSIM circuit simulator from Synopsys source code, and then conspired to destroy evidence. The ruling limits Nassda's defenses and raises the prospects of an injunction against HSIM.
TeraForm RTL tool gets new capabilities
News & Analysis  
6/14/2004   Post a comment
TeraSystems Inc. is offering three add-ons for its TeraForm register-transfer-level code handoff tool for low-power, high-performance or mixed-HDL design.
Le consortium Spirit élabore une nouvelle norme et accueille 15 nouveaux membres
News & Analysis  
6/14/2004   Post a comment
Le consortium Spirit (acronyme de Structure for Packaging, Integrating and Re-using IP within Tool-flows) a annoncé la semaine dernière qu’il avait élaboré un premier projet de norme pour sa propriété intellectuelle concernant un matériel d’encapsulation et de description et avait soumis cette proposition pour examen à un nombre accru de membres.
Les transactions dans le secteur de la CAO sont source d’innovation
News & Analysis  
6/14/2004   Post a comment
L’innovation dans le secteur de la CAO viendra encore des jeunes entreprises plutôt que des opérations de recherche et développement des entreprises publiques de CAO. Cette situation devrait inciter les grandes entreprises à acquérir les nouvelles sociétés qui se lancent sur le marché pour demeurer concurrentielles.
Actel enhances FPGA design suite
News & Analysis  
6/14/2004   Post a comment
Actel Corp. introduced the 6.0 version of its Libero Integrated Design Environment, promising a host of revised third-party tools and integration enhancements as well as a performance boost over the previous release, Libero 5.2.

À la recherche de stratégies d’alimentation des circuits intégrés pour résoudre les problèmes de complexité
News & Analysis  
6/14/2004   Post a comment
Les procédés de conception de puce sont de plus en plus audacieux ce qui ne facilite pas la gestion de l’alimentation et rend encore plus complexe les divers problèmes qui menacent de submerger l’industrie de la CAO, selon un groupe d’experts réuni à la Design Automation Conference (DAC) la semaine dernière à San Diego.
Les PDG d'entreprises de CAO proposent des solutions afin de valoriser l’industrie
News & Analysis  
6/14/2004   Post a comment
Les PDG des trois plus grands fournisseurs de CAO prédisent une meilleure situation économique avec la remontée du secteur des semi-conducteurs. Cependant, pour vraiment rehausser la valeur du secteur, les PDG affirment que les entreprises de CAO doivent veiller à ce que leurs outils soient interopérables et mettre au point des techniques qui améliorent le rendement et élèvent le niveau d’abstraction de la conception.
Mentor et Cadence se partagent les honneurs dans une étude sur les PCB
Survey  
6/14/2004   Post a comment
Mentor Graphics et Cadence Design Systems ont mérité les grands honneurs dans l’étude sur les cartes de circuits imprimés (PCB) et la conception assistée par ordinateur (CAO), mais Agilent EEsof a raflé le titre dans la catégorie satisfaction clientèle.
Verifikation wird wichtiger, aber Probleme bleiben
Product News  
6/14/2004   Post a comment
Das Finden und Beheben von Chip-Designfehlern wird immer schwieriger. Die für die Verifikation Verantwortlichen möchten daraus gerne Kapital schlagen. Ein Panel auf der diesjährigen Design Automation Conference (DAC) diskutierte die Möglichkeiten und Grenzen der Verifikation.
EDA-Branche am Scheideweg
News & Analysis  
6/14/2004   Post a comment
Die EDA-Branche steht vor grundlegenden Veränderungen. Die Herausforderungen des 65-nm-Nodes zwingen die Branche zu Kooperationen und Neuformierungen. Zu diesem Schluss kamen die Teilnehmer einer Podiumsdiskussion beim EDAC Business Forum, das im Rahmen der Design Automation Conference (DAC) im kalifornischen San Diego stattfand.
Analog-Designer: Bauchschmerzen mit Moore's Law
News & Analysis  
6/14/2004   Post a comment
Ist Moore's Law noch zu retten? Experten einer Podiumsdiskussion auf dem EDA-Fachtreffen Design Automation Conference (DAC) waren sich da nicht so sicher. Einig waren sich die Fachleute nur in einem Punkt: Es geht nicht mehr so weiter wie bisher.
NEC engineers advance hardware/software co-verification
News & Analysis  
6/11/2004   Post a comment
Claiming a new approach to hardware/software co-verification, researchers from NEC presented details about a combined simulation and emulation system at a Design Automation Conference paper session here. The approach integrates a C++ simulator with a low-cost FPGA-based emulator using shared register communications.
Reporter's notebook from the Design Automation Conference
News & Analysis  
6/11/2004   Post a comment
A reporter's notebook from the Design Automation Conference in San Diego.
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