How to improve verification planning Design How-To 6/27/2005 Post a comment Cadence Design Systems' Steve Brown walks you through the steps involved in putting together a good verification plan, including the development of specifications, objectives, coverage models, and metrics.
Premier accomplissement de la collaboration entre EVE et Novas News & Analysis 6/22/2005 Post a comment Emulation and Verification Engineering (EVE), fournisseur franco-américain de plates-formes de vérification fonctionnelle de circuits intégrés, a récemment annoncé les premiers fruits de sa collaboration avec Novas Software Inc., spécialiste des systèmes de débogage pour conceptions de puces complexes. Ensemble, ils sont parvenus à combiner la plate-forme de vérification matérielle ZeBu d’EVE avec le système de débogage automatique Verdi de Novas.
Zorian cited as Industrial Pioneer at DAC News & Analysis 6/21/2005 Post a comment Yervant Zorian, a pioneer in chip testing techniques, was awarded the 2005 IEEE Industrial Pioneer Award at the Design Automation Conference last week for his contributions to design-for-test technology.
Symphony EDA rolls out VHDL simulator Product News 6/21/2005 Post a comment Symphony EDA has introduced a VHDL simulation environment that the company claims reduces verification cycle time in complex chip designs while lowering the cost of ownership for high-performance simulation tools.
Top-down verification guides mixed-signal designs Design How-To 6/21/2005 Post a comment With mixed signal Design, the challenge is not in size, write Cadence veterans Ken Kundert and Henry Chang, reprising issued raised at last week's Design Automation Conference. The challenge is in the sheer difficulty of achieving the needed performance, they say. Analog designers are used to erecting circuit from the bottom up. But Top Down Verification not only aids design, but also puts modeling and simulation on a schedule. This article is from the June Planet Analog magazine folio.
Tool buffs up regression testing News & Analysis 6/20/2005 Post a comment Advanced Verification System (AVS), a verification management tool said to help speed IC regression testing, made its debut at last week's Design Automation Conference here.
EDA innovation costly, keynoter says News & Analysis 6/17/2005 Post a comment It can take six years and millions of dollars to go from a problem to proliferation of a full-fledged product, said EDA technologist Ron Rohrer, at a Design Automation Conference keynote speech Thursday.
DAC attendance up slightly in 2005 News & Analysis 6/17/2005 Post a comment Preliminary figures show that just over 6,000 registered attendees came to the 42nd Design Automation Conference (DAC) here, a slight increase over the 5,900 attendees at last year's DAC.
IC designers cite "Titanic" challenges News & Analysis 6/16/2005 Post a comment In a special session at the Design Automation Conference, four IC designers presented variability, reliability, power and methodology challenges not well served by existing tools and flows.
Linux comes with a price, says DAC panel News & Analysis 6/15/2005 Post a comment When it comes to stability for EDA, tool integration, support for mission-critical enterprise applications and binary compatibility, Linux has a long way to go, according to a panel discussion at the Design Automation Conference.
Designers adopt ESL, but tools are lacking News & Analysis 6/15/2005 Post a comment Chip designers are reporting success with electronic system level (ESL) design, but commercial EDA tools are falling short of what's needed, according to designers who spoke Tuesday at the Design Automation Conference.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...