Breaking News
Content tagged with Design Tools (EDA)
posted in June 2006
Page 1 / 2   >   >>
Bit-accurate C++ datatypes accelerate algorithmic simulation by 10-200x
News & Analysis  
6/30/2006   Post a comment
Mentor Graphics has announced the immediate availability of arbitrary-bit-width algorithmic C datatypes based on ANSI C++.
Bit-accurate C++ datatypes accelerate algorithmic simulation by 10-200x
Design How-To  
6/30/2006   Post a comment
Mentor has announced the immediate availability of arbitrary-bit-width algorithmic C datatypes based on ANSI C++.
Enhanced power integrity tool claims 2X speedup
News & Analysis  
6/30/2006   Post a comment
Power integrity EDA tool provider Apache Design Solutions released an enhanced version of the company's RedHawk-EV full-chip physical power integrity tool that claims to deliver at least a two-fold improvement in runtime speed and 40 percent less memory utilization compared to the preceding version.
Enhanced power integrity tool claims 2X speedup
News & Analysis  
6/30/2006   Post a comment
Power integrity EDA tool provider Apache Design Solutions released an enhanced version of the company's RedHawk-EV full-chip physical power integrity tool that claims to deliver at least a two-fold improvement in runtime speed and 40 percent less memory utilization compared to the preceding version.
ViASIC introduces 2-mask standard-metal structured ASIC fabric
Product News  
6/30/2006   Post a comment
ViASIC have introduced a new standard metal structured ASIC fabric intended for use in reconfigurable SOC designs.
Firm offers two-mask standard metal fabric
News & Analysis  
6/30/2006   Post a comment
Privately held EDA vendor ViASIC introduced DuoMask, billed as a high-density, two-layer standard-metal fabric for building configurable system-on-chip devices.
Altium offers 'drop in' tool for Nios II IDE
Product News  
6/29/2006   Post a comment
Altium announced the release of a new Tasking VX-toolset for the Nios II family of embedded processors from programmable logic supplier Altera.
Atmel's AVR32 gets $499 development kit support
Product News  
6/29/2006   Post a comment
Atmel is offering a $499 "program-and-go" development kit based on its AVR32-based AP7000 family of 32-bit digital signal controllers for multimedia, point-of-sale and small office/home office applications.
Ness, Pulsic set up India development center
News & Analysis  
6/29/2006   Post a comment
Global IT solutions provider Ness Technologies Inc. has established an extended development center (EDC) with Pulsic Ltd., a supplier of physical design solutions for analog, mixed signal and custom digital design. The development center is located at Ness' facility in Bangalore, India.
EDA returned to double-digit growth in Q1, EDAC says
News & Analysis  
6/29/2006   Post a comment
EDA revenue was up 10 percent year-to-year during the first quarter, the first time EDA posted double-digit growth in more than two years, according to a report by the EDA Consortium's Market Statistics Service.
First quarter Western Europe EDA revenue up 13%
News & Analysis  
6/29/2006   Post a comment
First quarter EDA revenue from Western Europe grew 13 percent year-to-year to reach $218 million, part of a strong quarter for EDA that saw worldwide revenue grow hit double digits for the first time in more than two years, according to the EDA Consortium.
How to speed FPGA debug with measurement cores and a mixed-signal oscilloscope
Design How-To  
6/28/2006   Post a comment
In which a packet communications system is analyzed, and glitches on an external serial channel are linked to a crashing state machine inside the FPGA.
Accelerated verification vendor collaborating with Indian firm
News & Analysis  
6/28/2006   Post a comment
Hardware-assisted verification provider Tharas Systems has formed a strategic alliance with Bangalore, India-based technology services provider Mirafra Technologies to collaborate on SystemVerilog support for Tharas' Hammer accelerated verification products.
Synopsys rolls USB 2.0 IP for TSMC low-power process
Product News  
6/28/2006   Post a comment
Synopsys released DesignWare USB 2.0 nanoPHY intellectual property (IP) for the Nexsys 90-nanometer low-power process from leading silicon foundry Taiwan Semiconductor Manufacturing Co. (TSMC).
Denali memory controller IP supports Cadence Encounter
News & Analysis  
6/28/2006   Post a comment
EDA and intellectual property vendor Denali Software has added support on its Databahn memory controller IP products for the Encounter RTL Compiler global synthesis tool from EDA market leader Cadence Design Systems.
Secure processor touts integrated RFID
Product News  
6/28/2006   Post a comment
Broadcom's BCM5890 secure processor with integrated radio frequency identification technology is designed to secure personal authentication transactions associated with physical access, logical access (into a PC or network) and contactless payment applications.
Synopsys packages concurrent timing, SI analysis
News & Analysis  
6/28/2006   Post a comment
Synopsys announced the availability of NanoTime, the company's next-generation transistor-level static timing analysis tool, offering concurrent timing and signal integrity analysis.
Datatypes accelerate algorithm validation by 10X, Mentor says
Product News  
6/27/2006   Post a comment
Mentor Graphics has made available new high-speed datatypes based on ANSI C++ that the company claims can accelerate algorithm validation by 10 fold.
TI targets digital power conversion with DSP controllers
Product News  
6/27/2006   Post a comment
Targeting digital power conversion, TI's new TMS320F28015 and F28016 controllers offer 60MHz of performance starting as low as $3.25. TI also offers a new Digital Power Development Kit, supported by hardware and software.
India preps registry for IC design, layout protection
News & Analysis  
6/27/2006   Post a comment
Six years after the Semiconductor Integrated Circuits Layout-Design Act of 2000, India is nearing completion of a registry to accept IC design and layout applications.
Integrated client/server-side IPSec VPN security toolkits target networking system developers
Product News  
6/27/2006   Post a comment
SafeNet's QuickSec 4.0 client and server toolkits enable adding IPSec and IKEv2 security to a full range of networking devices, including enterprise security gateways, enterprise-class PBX systems, desktop VPN clients, and mobile VPN platforms.
IC Compiler adds planning, power, DFM capabilities
Product News  
6/26/2006   Post a comment
Top tier EDA vendor Synopsys rolled out the latest version of its next-generation place-and-route tool, IC Compiler.
DFM startup snags $9.2 million in funding
News & Analysis  
6/26/2006   Post a comment
Design-for-manufacturing-focused EDA startup Pyxis Technology has raised $9.2 million in Series B funding from a group of venture capital firms led by Formative Ventures.
Cooley census: Magma users prefer anonymity
News & Analysis  
6/26/2006   Post a comment
While EDA users responding to Deepchip.com moderator John Cooley's latest "Everything Else EDA Census" offer positive reviews of most Magma Design Automation tools, Cooley flags an interesting trend: most prefer to remain anonymous.
DFM tool repairs IC layouts
Product News  
6/26/2006   Post a comment
There are many tools that analyze potential DFM problems in IC designs, but actually fixing the problems is another matter. Sagantec this week will take on that challenge with DFM-Fix, a standalone tool that claims to remove lithography "hot spots" in IC layouts.
Analog EDA startup offers modeling tool
Product News  
6/26/2006   Post a comment
Promising a better way to create analog/mixed-signal models, startup Lynguent is announcing its mission this along with ModLyng, its first product.
Startup tackles transistor-level IC design
News & Analysis  
6/26/2006   Post a comment
Startup Solido Design Automation this week is announcing its mission to provide "transistor-level design enhancement solutions" for analog/mixed-signal design, as well as custom digital and memory design.
Constraint-driven physical design speeds IC convergence
News & Analysis  
6/26/2006   Post a comment
Authors from Cadence Design Systems call for a new, constraint-driven physical design methodology for ICs at 65 nm and below.
Tool suite hits the market for 65-nm Virtex-5 FPGAs
Product News  
6/26/2006   Post a comment
Xilinx's 8.2i Integrated Software Environment (ISE) tool suite supports its line of 65-nm Virtex-5 domain-optimized FPGAs. Leveraging the high-performance features of the Virtex-5 ExpressFabric technology, the ISE 8.2i design environment boosts performance by 30% compared with previous-generation FPGAs.
ARC, Cadence extend platform collaboration
Product News  
6/26/2006   Post a comment
ARC International and Cadence Design Systems, Inc. have integrated support of the Cadence Encounter IC design platform into ARCís ARChitect processor configuration tool.
European IC design shows solid growth
News & Analysis  
6/26/2006   Post a comment
The number of IC design companies in Europe increased by 12.7 percent over the past year, according to just published research from consultancy group Future Horizons.
Cadence intros ARM verification kit
News & Analysis  
6/26/2006   Post a comment
Adding a new level of specificity to its endeavor to offer customers customized design kits, Cadence Design Systems rolled out a functional verification kit specifically for technology from ARM Holdings.
UMC claims wide interest in 65-nm
News & Analysis  
6/23/2006   Post a comment
Top tier silicon foundry United Microelectronics Corp. said a pair of customers have qualified 65-nanometer designs and are in production at the foundry, with eight other customers engaged and 11 product tape-outs expected by the end of summer 2006.
How to implement an open IP encryption flow
Design How-To  
6/23/2006   Post a comment
Synplicity are proposing an open IP encryption flow that will permit industry-wide interoperability, and that can be extended to cover a wide range of applications.
Xilinx receives SEC inquiry on stock options
News & Analysis  
6/23/2006   Post a comment
Programmable logic device supplier Xilinx Inc. said that the Securities and Exchange Commission is conducting an informal inquiry into the company' practices, procedures, and disclosures on stock options grants.
Rounding Algorithms 101 Redux
Design How-To  
6/22/2006   Post a comment
An alternative introduction to a variety of rounding algorithms such as round-half-up, round-half-down, round-half-even, round-ceiling, round-floor...
European foundry's DFM flow supports yield optimization tool
News & Analysis  
6/22/2006   Post a comment
The silicon foundry business unit of austriamicrosystems has added support for Munich, Germany-based EDA startup MunEDA's Wicked design-for-manufacturing tool to its DFM reference flow.
Feature claims to break software validation bottleneck
News & Analysis  
6/22/2006   Post a comment
In a bid to address difficulties created by the differing models typically contained within ESL environments, startup Carbon Design Systems plans to introduce new functionality for its SOC-VSP virtual system prototyping product line at next month's DAC.
Core-assisted approach accelerates debug of FPGA DDR II interfaces
Design How-To  
6/22/2006   Post a comment
In this "How To" tutorial, a debug methodology is described and applied to a real FPGA-based DDR II high-speed memory controller debug example.
Accellera transfers OpenKit work to Si2
News & Analysis  
6/21/2006   Post a comment
EDA standards organization Accellera is transferring the materials associated with its three-year old OpenKit Initiative to Si2 for further development.
Startup changing product name
News & Analysis  
6/19/2006   Post a comment
EDA startup Nascentric is changing the name of its simulation and analysis tool from Nascim to AuSIM (pronounced AWE-sim).
Aprio names VP of sales
News & Analysis  
6/19/2006   Post a comment
Design-for-manufacturing tool startup Aprio Technologies has named industry veteran Mark Fournival vice president of worldwide sales.
Emulation Extension Chip eases high-speed automotive embedded processor integration
Design How-To  
6/19/2006   Post a comment
Debugging and calibrating are becoming more difficult as microcontroller clock speeds increase. An embedded emulation device provides designers true visibility inside highly integrated SoC microcontrollers.
Denali rolls PCI Express design IP
News & Analysis  
6/19/2006   Post a comment
EDA and intellectual property vendor Denali Software announced availability of a fully featured design core for PCI Express technology and said the product has already been successfully incorporated into production silicon.
Altera offering Stratix II IP encryption solution
News & Analysis  
6/19/2006   Post a comment
Programmable logic supplier Altera has made available a comprehensive intellectual property encryption solution to improve security of Stratix II FPGA design.
Synplicity pushing open IP encryption methodology standard
Product News  
6/19/2006   Post a comment
Synplicity is offering, free of charge, a non-proprietary intellectual property encryption flow that permits industry-wide interoperability.
Synplicity pushing open IP encryption methodology standard
Product News  
6/19/2006   Post a comment
Synplicity is offering, free of charge, a non-proprietary intellectual property encryption flow that permits industry-wide interoperability.
Lattice offers IP portfolio for LatticeSC Extreme FPGAs
Product News  
6/19/2006   Post a comment
Programmable logic supplier Lattice Semiconductor announced the immediate availability of an intellectual property portfolio for the LatticeSC Extreme Performance FPGA family.
Integrated software development tools support Blackfin DSP
Product News  
6/19/2006   Post a comment
ADI's multimedia starter kit offers development tools for Blackfin DSP. The kit is supported by the integrated software development and debugging environment.
Sequential equivalence checking for RTL models
Design How-To  
6/19/2006   Post a comment
Authors from Calypto Design Systems show what sequential equivalence checking is, how it's applied across RTL models, and how it can be used most effectively.
Page 1 / 2   >   >>


Flash Poll
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Rishabh N. Mahajani, High School Senior and Future Engineer

Future Engineers: Donít 'Trip Up' on Your College Road Trip
Rishabh N. Mahajani, High School Senior and Future Engineer
Post a comment
A future engineer shares his impressions of a recent tour of top schools and offers advice on making the most of the time-honored tradition of the college road trip.

Max Maxfield

Juggling a Cornucopia of Projects
Max Maxfield
5 comments
I feel like I'm juggling a lot of hobby projects at the moment. The problem is that I can't juggle. Actually, that's not strictly true -- I can juggle ten fine china dinner plates, but ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
29 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Karen Field

July Cartoon Caption Contest: Let's Talk Some Trash
Karen Field
128 comments
Steve Jobs allegedly got his start by dumpster diving with the Computer Club at Homestead High in the early 1970s.

latest comment mhrackin Where's the "empty bin" link?
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)