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Content tagged with Design Tools (EDA)
posted in June 2007
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Agilent releases modeling design system for antenna systems
Product News  
6/28/2007   Post a comment
Agilent has released its Antenna Modeling Design System (AMDS), which is a 3D dedicated design, modeling and verification tool for antenna systems and placement.
Synopsys reaffirms support for Vera
News & Analysis  
6/28/2007   Post a comment
Even though Synopsys is heavily pushing SystemVerilog as a unified design and verification language, the company is reaffirming support for its own Vera testbench language.
EE Times updates list of emerging startups
News & Analysis  
6/28/2007   Post a comment
The EE Times 60 Emerging Startups list, first published in April 2004, has been updated to version 6.0 to reflect the latest corporate, commercial, technology and market conditions.
Ciranova plans persistent p-cell donation
News & Analysis  
6/27/2007   Post a comment
Taking another step towards analog EDA interoperability, Ciranova Inc. is planning to donate caching technology for persistent parameterized cells (p-cells) to the Open Access Coalition.
Mentor Graphics Delivers Verification Solutions for ARM-based Wireless and Multimedia Applications
Product News  
6/27/2007   Post a comment
Mentor's iSolve family of vertical market solutions now includes two new ARM processors, the ARM11 MPCore multiprocessor and the ARM1176JZF-S processor.
CAD benchmarks may improve MP3/MPEG decoders
News & Analysis  
6/27/2007   Post a comment
An effort to develop public domain benchmarks for CAD research may lead to more energy-efficient MP3 and MPEG2 decoders, according to researchers at McMaster University in Ontario, Canada.
New kit cuts development time for industry's latest non-volatile FPGAs
Product News  
6/26/2007   Post a comment
Xilinx delivers Spartan-3AN starter kit for rapid evaluation of consumer communication infrastructure and industrial applications.
Startup seeks litho-friendly 'route' to success
News & Analysis  
6/26/2007   Post a comment
EDA startup Lizotech is preparing a "correct by construction" IC router that claims to eliminate lithography hot spots, basing design for manufacturability (DFM) on prevention rather than repair.
Commentary: SystemVerilog enables design with verification
Blog  
6/26/2007   Post a comment
SystemVerilog is closely linked to the continuing evolution from "design for verification" to "design with verification."
Functional Qualification
Design How-To  
6/26/2007   Post a comment
Functional qualification is the first technology to provide an objective answer to this fundamental question. It is an essential addition to the increasingly challenging task of delivering functionally correct silicon on time and on budget.
Agilent Announces Integrated Verification Toolkit for Signal Integrity Design
Product News  
6/26/2007   Post a comment
Intended for use with Agilent's Advanced Design System (ADS) EDA software platform, the new toolkit identifies and analyzes sources of performance-degrading jitter in multi-Gigabit communication link designs.
DAC: IP and Power. Then and now
Blog  
6/25/2007   Post a comment
DAC left issues in Intellectual Property quality and Power Format standardization unresolved.
Xilinx delivers latest ISE with lower memory requirements and new OS support
Product News  
6/25/2007   Post a comment
Latest release of Xilinx ISE design tools allows designers to meet performance goals with greater certainty and reach design closure in less time.
Analog behavioral models reduce mixed-signal LSI verification time
Design How-To  
6/22/2007   Post a comment
Selective use of analog behavioral models instead of SPICE elements can greatly speed up simulation
ARC Introduced New Modeling and Simulation Products
Product News  
6/22/2007   Post a comment
ARC International introduced two new development tools that add to the growing portfolio of EDA solutions used to create system-on-chips (SoCs) from ARC and its partner network.
Generate efficient vehicle dynamic models - right down to the tires: Part 2 - simulation and validation
Design How-To  
6/22/2007   Post a comment
Software that develops vehicle dynamic equations symbolically produces computationally efficient simulation code that is ideal for real-time applications for systems with arbitrary topology.
Software-Intensive ASICs/ASSPs Demand Integrated Prototyping Solutions
Design How-To  
6/22/2007   Post a comment
FPGA-based prototypes are an ideal software development platform for several reasons. Increased simulation speed, lower development costs, and improved quality of design.
Generate efficient vehicle dynamic models - right down to the tires: Part 1 - procedures and system topology
Design How-To  
6/21/2007   Post a comment
Software that develops vehicle dynamic equations symbolically produces computationally efficient simulation code that is ideal for real-time applications for systems with arbitrary topology.
Asynch FPGA vendor in-sync with Mentor
News & Analysis  
6/20/2007   Post a comment
Asynchronous FPGA startup Achronix Semiconductor Corp. (San Jose, Calif.) has announced a technology partnership and OEM agreement with EDA company Mentor Graphics Corp. (Wilsonville, Ore.).
Xilinx announces TD-SCDMA digital front-end reference design
Product News  
6/20/2007   Post a comment
New reference design from Xilinx provides customers with significant head-start in development of multi-channel digital up and down conversion solutions for TD-SCDMA radios
MPSoC Kicks Off Next Week in Japan
News & Analysis  
6/19/2007   Post a comment
Multi-Processor SoC (MPSoC), co-sponsored by the IEEE Council on Electronic Design Automation (CEDA), will take place June 25-29 in Hyogo, Japan.
Cadence Improves Allegro PCB Technology for RF Printed-Circuit-Board Design
Product News  
6/19/2007   3 comments
Cadence has added RF technology and design methodology to its Alegro PCB Design XL and GXL product offerings.
EDA Shocked Into Action
Blog  
6/18/2007   Post a comment
Coverage of the EDA industry is shrinking to the levels justified by advertising revenues, endangering the quality of coverage. Changes are required by both EDA vendors and publishers.
Actel offers 'Smart' FPGA design
Product News  
6/18/2007   Post a comment
Actel Corp. is promising to bring FPGA design to a higher level of abstraction with SmartDesign, which generates synthesizable code from graphical block diagrams.
Aart De Geus Awarded the 2007 IEEE Robert N. Noyce Medal
News & Analysis  
6/18/2007   Post a comment
The IEEE presented Aart de Geus with its 2007 IEEE Robert N. Noyce Medal at its Honors Ceremony in Philadelphia, Pa on June 16th.
Change is the only constant
Blog  
6/18/2007   Post a comment
It's hard to read news of the electronics industry these days and not want to develop a drinking problem.
How to keepengineers happy
News & Analysis  
6/18/2007   Post a comment
It's harder than it's been in years for electronics companies to hold onto engineers as market dynamics have pushed unemployment rates below 2 percent. How does a company keep its engineers from seeking greener pastures? What makes an organization the kind of place an engineer wants to work?

Design Constraint Verification and Validation: A New Paradigm
Design How-To  
6/18/2007   Post a comment
While chip design, functional verification, timing verification and manufacturing have become highly automated, the writing and verification of design constraints has been largely a tedious, manual process. But Software can manage, verify and even create design constraints.
ARC buys Tenison for simulation capability
News & Analysis  
6/15/2007   Post a comment
ARC International has purchased Tenison in order to expand its portfolio to include verification capabilities.
Commentary: Determining the cost of power
News & Analysis  
6/15/2007   Post a comment
Vic Kulkarni, Sequence Design CEO, presents some suggestions for determining the true cost of power in a system-on-chip design.
The Week after DAC: some lingering thoughts
Blog  
6/15/2007   Post a comment
DAC continues to be the true mirror of the state of EDA.
Oasis moves slowly as GDSII replacement
News & Analysis  
6/14/2007   Post a comment
The Oasis file format is seeing slower adoption than expected as a GDSII replacement, and industry observers have some ideas why that might be happening.
Ansoft releases 3D full-wave electromagnetic field simulation software
Product News  
6/13/2007   Post a comment
This industry-standard software for 3D full-wave electromagnetic field simulation raises the bar for accuracy, capacity and performance.
Report: Virtual system prototyping growing quickly
News & Analysis  
6/13/2007   Post a comment
Virtual system prototyping is the fastest growing segment of the electronic system level (ESL) market, according to a research report from the Venture Development Corporation (VDC).
ST readies design platform, SoCs for 45-nm process
News & Analysis  
6/13/2007   Post a comment
STMicroelectronics is readying a 45-nm CMOS design platform for SoCs targeting low-power, wireless and portable consumer applications and the company says the process has been used to tape-out a tightly integrated demonstrator SoC device earlier than anticipated.
New CEO guides Bluespec's changing strategy
News & Analysis  
6/12/2007   Post a comment
Charlie Hauck has become Bluespec CEO as the electronic system level (ESL) synthesis provider moves beyond point tools, and expands into design services and intellectual property.
Software Verification and Debug in the MPSoC Era
Design How-To  
6/12/2007   Post a comment
The availability of multicore chips are demanding the use of parallel programming tchniques. But debugging tools and methods for parallel software and hardware systems lag in development.
Competitors disdain Mentor's Sierra acquisition
News & Analysis  
6/11/2007   Post a comment
Synopsys, Cadence Design Systems, and Magma Design Automation say they aren't worried about Mentor Graphics' acquisition of IC placement and routing provider Sierra Design Automation.
Mentor Ate The Donut
Blog  
6/11/2007   Post a comment
Mentor acquired Sierra Design Automation to complete its Design to Manufacturing flow for leading edge IC designs.
TimingDesigner enhanced with pre-assembled component timing diagrams
Product News  
6/8/2007   Post a comment
EMA Design Automation has released TimingDesigner 9.0, featuring design kits with assembled diagrams and libraries for commonly used parts and interface protocol standards, and program modifications to accommodate the latest features of the newest operating systems.
DAC Blogs: New startups, attendance down, private equity rumors
News & Analysis  
6/8/2007   Post a comment
EE Times software editor Richard Goering filed blog entries from the Design Automation Conference about previously unknown EDA startups, lackluster attendance, private equity buyout rumors, and a slowdown in design for manufacturability (DFM) activity.
EDA methodologies aid biological research
News & Analysis  
6/8/2007   Post a comment
Principles borrowed from electrical engineering are speeding research into synthetic biology, said researchers at a special session at the Design Automation Conference Thursday (June 7).
DAC panelists call for IP reuse standards
News & Analysis  
6/8/2007   Post a comment
Design Automation Conference panelists agreed on the need for standards for silicon intellectual property (IP) reuse, but were short on details about taking specific steps toward that goal.
Keynote: EDA brings life to synthetic biology
News & Analysis  
6/7/2007   Post a comment
Manufacturing and design approaches developed for microelectronics can apply to the emerging field of synthetic biology, said Design Automation Conference keynote speaker Jan Rabaey, professor at the University of California at Berkeley.
DAC should consider combining with Semicon: Magma CEO
News & Analysis  
6/6/2007   Post a comment
Struggling with attendance and shrinking exhibitors, the Design Automation Conference should consider merging with another show, a CEO said.
IC designers call for early power validation
News & Analysis  
6/6/2007   Post a comment
Early power-aware IC validation is slowly becoming a reality, but better tools and models are needed, according to IC designers who spoke at a Design Automation Conference panel.
Synopsys awards competitors for low power effort
News & Analysis  
6/6/2007   Post a comment
Synopsys has given its annual Tenzing Norgay interoperability award to four companies, including competitors Mentor Graphics and Magma Design Automation, for work with Synopsys in developing the Unified Power Format (UPF).
Analysis: Synplicity's 'Hardi' ASIC prototyping play
News & Analysis  
6/6/2007   Post a comment
With its purchase of ASIC prototyping vendor Hardi AB, Synplicity is taking an approach to the ASIC verification market that avoids direct competition with big EDA vendors.
Microwave tool heats up extraction
Product News  
6/6/2007   Post a comment
Applied Wave Research Inc. has released Microwave Office 2007 and Visual System Simulator 2007, the latest versions of its RF design tool suites.
DAC panelists eye EDA in 2017
News & Analysis  
6/5/2007   Post a comment
The EDA industry should enjoy respectable growth during the next ten years, but must adapt to new challenges, said panelists at the Design Automation Conference Tuesday.
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