Synopsys reaffirms support for Vera News & Analysis 6/28/2007 Post a comment Even though Synopsys is heavily pushing SystemVerilog as a unified design and verification language, the company is reaffirming support for its own Vera testbench language.
Functional Qualification Design How-To 6/26/2007 Post a comment Functional qualification is the first technology to provide an objective answer to this fundamental question. It is an essential addition to the increasingly challenging task of delivering functionally correct silicon on time and on budget.
Asynch FPGA vendor in-sync with Mentor News & Analysis 6/20/2007 Post a comment Asynchronous FPGA startup Achronix Semiconductor Corp. (San Jose, Calif.) has announced a technology partnership and OEM agreement with EDA company Mentor Graphics Corp. (Wilsonville, Ore.).
EDA Shocked Into Action Blog 6/18/2007 Post a comment Coverage of the EDA industry is shrinking to the levels justified by advertising revenues, endangering the quality of coverage. Changes are required by both EDA vendors and publishers.
Actel offers 'Smart' FPGA design Product News 6/18/2007 Post a comment Actel Corp. is promising to bring FPGA design to a higher level of abstraction with SmartDesign, which generates synthesizable code from graphical block diagrams.
How to keepengineers happy News & Analysis 6/18/2007 Post a comment
It's harder than it's been in years for electronics companies to hold onto engineers as market dynamics have pushed unemployment rates below 2 percent. How does a company keep its engineers from seeking greener pastures? What makes an organization the kind of place an engineer wants to work?
Design Constraint Verification and Validation: A New Paradigm Design How-To 6/18/2007 Post a comment While chip design, functional verification, timing verification and manufacturing have become highly automated, the writing and verification of design constraints has been largely a tedious, manual process.
But Software can manage, verify and even create design constraints.
ST readies design platform, SoCs for 45-nm process News & Analysis 6/13/2007 Post a comment STMicroelectronics is readying a 45-nm CMOS design platform for SoCs targeting low-power, wireless and portable consumer applications and the company says the process has been used to tape-out a tightly integrated demonstrator SoC device earlier than anticipated.
Keynote: EDA brings life to synthetic biology News & Analysis 6/7/2007 Post a comment Manufacturing and design approaches developed for microelectronics can apply to the emerging field of synthetic biology, said Design Automation Conference keynote speaker Jan Rabaey, professor at the University of California at Berkeley.
Synopsys awards competitors for low power effort News & Analysis 6/6/2007 Post a comment Synopsys has given its annual Tenzing Norgay interoperability award to four companies, including competitors Mentor Graphics and Magma Design Automation, for work with Synopsys in developing the Unified Power Format (UPF).
DAC panelists eye EDA in 2017 News & Analysis 6/5/2007 Post a comment The EDA industry should enjoy respectable growth during the next ten years, but must adapt to new challenges, said panelists at the Design Automation Conference Tuesday.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments