Design Con 2015
Breaking News
Content tagged with Design Tools (EDA)
posted in June 2010
Page 1 / 2   >   >>
Dolphin Integration rolls panoply of IPs to reduce 65nm silicon area
Product News  
6/29/2010   Post a comment
EDA and IP company Dolphin Integration SA has introduced a panoply of silicon IPs optimized for high density so that designers can increase the density of their SoC by up to 10 percent.
Using FPGA prototyping board as an SoC verification and integration platform
Design How-To  
6/29/2010   Post a comment
Size of new designs has grown so much that it easily allows creation of the entire system containing microprocessor unit and peripherals on one chip. This paper presents one practical implementation of Prototyping Board Verification and Integration Platform.
Designing systems for extreme environments
Design How-To  
6/28/2010   Post a comment
Designing embedded systems destined for extreme environments, such as 1 mile below the surface of an ocean, adds a layer of complexity and difficulty for the designer. Nate Holmes of National Instruments describes some common challenges and latest tools and approaches to issues like power and test that can aid designers in creating successful systems headed for tough spots.
SPICE Simulation of Transmission Lines by the Telegrapher's Method (Part 1 of 3)
Design How-To  
6/28/2010   Post a comment
Understand the underlying principles and end up with a relatively simple sub-circuit which offers full frequency dependence and fidelity
Case study: Cost-effective and rapid audio headset design and verification
Design How-To  
6/22/2010   Post a comment
This article describes a development and verification platform used to shorten audio headset design, development, and test cycles.
Filter Design using the Million Monkeys Method
Design How-To  
6/22/2010   1 comment
The Filter Wizard focuses on cool things you can do with a spreadsheet that most circuit simulators cannot.
COMMENTARY: From Microprocessor to Microcontroller to ???
Blog  
6/21/2010   1 comment
Meng He and Andrew Siska look at the evolution of embedded processing, and explore the implications of programmable system on chip architectures to its future direction..
ICs - Imperas releases fast models of PowerPC processors Through OVP Initiative
News & Analysis  
6/20/2010   Post a comment
Imperas has released fast models of PowerPC processors. These models work with the OVP simulator, OVPsim, where they have shown performance reaching over one thousand million instructions per second (MIPS).
Cadence closes Denali acquisition
News & Analysis  
6/17/2010   Post a comment
EDA supplier Cadence Design Systems has closed the $315 million acquisition of memory IP vendor Denali Software, the company announced.
Student Entrepreneur: gets an idea
Blog  
6/17/2010   Post a comment
Simon Barker pitches to a video camera and then decides on an iPad-related side project while he completes his PhD.
DAC: IC design bound for cloud computing
News & Analysis  
6/17/2010   4 comments
Cloud computing for EDA work may still be in the clouds but in three to five years it will occupy up to 20 percent of design transactions between major EDA vendors and their customers.
DAC panel: Disruptive 3-D vias will follow applications
News & Analysis  
6/17/2010   Post a comment
At the Design Automation Conference here key thought leaders in the area of 3-D packaging made an attempt to forecast a roadmap for 3-D thru silicon vias interconnects.
Debug will get your attention, sooner or later
Design How-To  
6/17/2010   Post a comment
Debug will get your attention one way or another. If you give it attention early in the development cycle, it will reduce the amount of time spent on debug later and in future designs as well as reducing the uncertainty related to debug.
IRIS adds two Stratix IV FPGA-based boards
Product News  
6/17/2010   Post a comment
IRIS Technologies Inc. (Richardson, Texas) has released two boards based on the Altera Stratix IV 820 devices. These contain the largest FPGA on the market and provide flexibility for development and prototyping products.
Azuro's Rubix improves timing optimization
Product News  
6/17/2010   Post a comment
Power-focused EDA startup Azuro Inc. (Santa Clara, Calif.) claimed that the latest version of its Rubix clock concurrent optimization tool delivers a 15-percent increase in clock frequency.
Group aims to set standards for multicore tools
News & Analysis  
6/17/2010   Post a comment
The Multicore Association has formed a new work group to tackle the problem of incompatible software development tools for multicore processors and expects to have a draft standard for one or more common data format and a Linux-based reference implementation of its work within a year.
Online MOSFET thermal simulation tool offers increased simulation accuracy
Product News  
6/16/2010   1 comment
Vishay Intertechnology has improved its ThermaSim online MOSFET thermal simulation tool to provide increased simulation accuracy, efficiency, and user friendliness.
SOFTWARE TOOLS - CoFluent Design and Docea Power team up to accelerate power optimization
News & Analysis  
6/16/2010   Post a comment
CoFluent Design's CoFluent Studio and Docea Power's Aceplorer are now part of an interoperable solution that accelerates power exploration and optimization of electronic systems, allowing systems architects to optimize power usage more efficiently.
Magillem raises $1.5 million in SPO
News & Analysis  
6/16/2010   Post a comment
Paris-based Magillem SA announced it has raised $1.5 million in a secondary public offering on the Euronext Paris Free market led by Arkeon Finances.
Azuro enhances clock tree synthesis tool
Product News  
6/16/2010   Post a comment
Power-focused EDA startup Azuro Inc. (Santa Clara, Calif.) has introduced version 5.2 of its PowerCentric clock tree synthesis tool for digital standard cell-based chip designs.
Product How-To: Making USB Flash drives secure: Why and How?
News & Analysis  
6/16/2010   Post a comment
This article is on the reasons for and the method of making USB flash drives secure.
Industry collaboration to feed future chip designs
News & Analysis  
6/16/2010   Post a comment
Chip design companies need to redefine relationships with their manufacturing partners, and foundries must create a new model that brings manufacturing and design into an integrated and collaborative process.
Mobile chipset users get help from iCEcube2 development tool
Product News  
6/15/2010   Post a comment
The iCEcube2 EDA development tool is a result of SiliconBlue's development partnership with Synopsys Inc. and is intended to bring the stable FPGA synthesis of Synplify Pro software to mobile designers.
Forte's Cynthesizer joins TSMC Reference Flow 11.0
Product News  
6/15/2010   Post a comment
High-level synthesis EDA vendor Forte Design Systems announced that its Cynthesizer SystemC high-level synthesis tool has been validated by TSMC for Reference Flow 11.0 inclusion.
CEA-Leti, Docea team on next gen 3D-IC design
News & Analysis  
6/15/2010   Post a comment
The Electronics and Information Technology Laboratory of the CEA (CEA-Leti) of France and Docea Power SAS (Moirans, France) announced they have sealed a laboratory agreement to combine their expertise in 3D silicon integration as well as thermal and low power design.
Khronos upgrades parallel programming standard
News & Analysis  
6/15/2010   Post a comment
The Khronos Group, an industry consortium focused on developing multimedia standards and application programming interfaces (APIs), has released version 1.1 of the OpenCL specification, a royalty-free standard for parallel programming of processors.
Altos expands corporate structure, global presence
News & Analysis  
6/15/2010   Post a comment
Library characterization startup Altos Design Automation Inc. announced it has doubled headquarters space in Campbell, Calif., added John Ennis as worldwide vice president of sales and established presence in Beijing, China, to address customer demand and market potential.
TSMC, Tela trim logic die area by 15%
News & Analysis  
6/15/2010   Post a comment
Taiwan Semiconductor Manufacturing Co. Ltd. has introduced its so-called Slim Library of standard cells, which reduces system-on-chip (SoC) routed logic block area by 15 percent compared to blocks routed through conventional standard cell libraries.
Reducing switching power with intelligent clock gating
Design How-To  
6/15/2010   3 comments
Xilinx has introduced automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30 percent for Virtex-6 and Spartan-6 FPGA designs. Intelligent clock-gating optimizations are automatically performed on the entire design, introduce no new tools or steps to the flow, and generate no changes to the existing logic or to the clocks that alter the behavior of the design. And, in most cases, the timing is also preserved.
Full Altera Stratix IV family in volume production
News & Analysis  
6/14/2010   Post a comment
Programmable logic vendor Altera has commenced production shipments of the highest density member of its 40-nm Stratix IV FPGA family, the Stratix IV E EP4SE820. All members the Stratix IV family are now shipping in volume, according to the company.
DESIGN TOOLS - BEEcube launches BEE4, a full-speed FPGA prototyping platform
News & Analysis  
6/14/2010   Post a comment
BEE4 is the fourth generation of BEE (Berkeley Emulation Engine), a full-speed FPGA prototyping platform from BEEcube, Inc. BEE4 is designed to address one of the biggest problems with multiple FPGA platforms used for system verification and validation.
eSilicon links with S3 for design service
News & Analysis  
6/14/2010   Post a comment
Design and manufacturing services provider eSilicon Corp. has teamed up with design services and IP licensor S3 Group for a worldwide deal.
The Stroud number in engineering
Blog  
6/14/2010   Post a comment
John M. Stroud was a psychologist who studied the decision processes of people to determine whether such processes have measurable quantities.
EDA DesignLine's "what's new" list at DAC!
Blog  
6/11/2010   1 comment
The countdown to the 47th Design Automation Conference (DAC) in Anaheim, Calif., has begun. Before you get to the Convention Center, have a look at EDA DesignLine's list of EDA products that will be introduced and showcased at the show.
IMEC set to take transistors 'sub-threshold'
News & Analysis  
6/11/2010   Post a comment
Researchers at IMEC are investigating the operation of transistors below the threshold voltage. The goal is to further improve power efficiency.
Analysis: Acquisitions reflect broadening view of EDA
News & Analysis  
6/11/2010   2 comments
Recent acquisition activity by large EDA vendors represents the most recent and perhaps boldest evidence of a broadening focus that steps away from a "myopic view of what EDA is that was killing the industry," according to a prominent EDA analyst.
Synopsys buys Synfora assets
News & Analysis  
6/10/2010   Post a comment
In its second major acquisition announcement in one day, EDA and IP vendor Synopsys said it has acquired technology, engineering resources and other assets of high-level synthesis EDA vendor Synfora Inc. The financial terms of the deal, which closed Thursday, were not disclosed.
Update: Synopsys to buy Virage Logic for $315M
News & Analysis  
6/10/2010   1 comment
EDA and IP vendor Synopsys Inc. said it signed a definitive agreement to acquire IP provider Virage Logic for $315 million in cash.
ARM shares spike again
News & Analysis  
6/10/2010   1 comment
Shares in processor intellectual property licensor ARM Holdings plc spiked on Thursday taking the stock up above 300 pence a share from an opening price of 273.4 pence.
Time is right for clockless design
Design How-To  
6/10/2010   11 comments
The demands of consumer applications to combine high performance with low power are forcing continued innovation in how the chips that power them are designed. After many years in the research labs, asynchronous technology has arrived as a viable approach, thanks to an emerging set of tools and capabilities from specialized suppliers who understand that the technology must not just work in concept, but also meet certain market requirements in order to be more broadly accepted and used.
SOFTWARE TOOLS - Artisan Studio 7.2 adds role-based editions, DoDAF support
News & Analysis  
6/9/2010   Post a comment
Atego's Artisan Studio 7.2 development tool suite adds role-based editions, DoDAF support. Other enhancements include DoDAF support for UPDM, 80 new metric reports for Artisan Studio Reviewer, usability improvements to Artisan Publisher, and a new model comparison tool.
AMS chooses Nangate for digital cell library IP development
News & Analysis  
6/9/2010   Post a comment
austriamicrosystems AG (AMS) announced it has implemented the Library Creator, Nangate's integrated digital cell library creation and characterization solution, to increase library development productivity and improve its IP portfolio performance and quality.
Teklatech sets foot in Japan
Product News  
6/9/2010   Post a comment
EDA startup Teklatech A/S (Copenhagen, Denmark) announced it has expanded its worldwide presence with the appointment of Japanese representation.
First MRAM-based FPGA taped-out
Product News  
6/9/2010   Post a comment
Menta SAS and LIRMM have taped out what they describe as the of worlds first MRAM-based FPGA which has patent-protected circuitry enabling compact integration of MRAM and embedded-FPGA solutions.
Xilinx licenses synthesis technology from EDA startup
News & Analysis  
6/9/2010   Post a comment
Market-leading programmable logic vendor Xilinx has signed a multi-year strategic licensing agreement to use chip synthesis technology from EDA vendor Oasys Design Systems.
Infineon adotps Ceva DSP core for wireless platforms
News & Analysis  
6/8/2010   Post a comment
Intellectual property licensor Ceva Inc. has licensed its dual MAC, 32-bit CEVA-TeakLite-III DSP core to Infineon Technologies for use in future mobile phone and modem platforms.
TSMC rolls two reference flows
News & Analysis  
6/8/2010   Post a comment
As expected, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has rolled out two reference flows to speed up new designs in the foundries.
Docea, CoFluent to accelerate power exploration of system design
News & Analysis  
6/8/2010   Post a comment
After Magillem SA, Docea Power SAS (Moirans, France) is announcing a collaboration with CoFluent Design (Nantes, France) to accelerate power exploration and optimization of electronic systems.
Achieving verification closure with resource and time constraints
Design How-To  
6/8/2010   Post a comment
This paper discusses the challenges in creating an agile verification team and the tool and methodology options available for supporting such a team.
Synphony HLS adds support for Xilinx Virtex-6 FPGAs
Product News  
6/8/2010   Post a comment
Synopsys Inc. has added optimized support for Xilinx Virtex-6 FPGAs to its Synphony HLS (High Level Synthesis) product.
Page 1 / 2   >   >>


Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Curiosity Killed the Cat (Just Call Me Mr. Curiosity)
Max Maxfield
23 comments
My wife, Gina The Gorgeous, loves animals. She has two stupid dogs and two stupid cats. How stupid are they? Well, allow me to show you this video of the dogs that I made a couple of years ...

Martin Rowe

No 2014 Punkin Chunkin, What Will You Do?
Martin Rowe
Post a comment
American Thanksgiving is next week, and while some people watch (American) football all day, the real competition on TV has become Punkin Chunkin. But there will be no Punkin Chunkin on TV ...

Rich Quinnell

Making the Grade in Industrial Design
Rich Quinnell
13 comments
As every developer knows, there are the paper specifications for a product design, and then there are the real requirements. The paper specs are dry, bland, and rigidly numeric, making ...

Martin Rowe

Book Review: Controlling Radiated Emissions by Design
Martin Rowe
1 Comment
Controlling Radiated Emissions by Design, Third Edition, by Michel Mardiguian. Contributions by Donald L. Sweeney and Roger Swanberg. List price: $89.99 (e-book), $119 (hardcover).