Designing systems for extreme environments Design How-To 6/28/2010 Post a comment Designing embedded systems destined for extreme environments, such as 1 mile below the surface of an ocean, adds a layer of complexity and difficulty for the designer. Nate Holmes of National Instruments describes some common challenges and latest tools and approaches to issues like power and test that can aid designers in creating successful systems headed for tough spots.
DAC: IC design bound for cloud computing News & Analysis 6/17/2010 4 comments Cloud computing for EDA work may still be in the clouds but in three to five years it will occupy up to 20 percent of design transactions between major EDA vendors and their customers.
IRIS adds two Stratix IV FPGA-based boards Product News 6/17/2010 Post a comment IRIS Technologies Inc. (Richardson, Texas) has released two boards based on the Altera Stratix IV 820 devices. These contain the largest FPGA on the market and provide flexibility for development and prototyping products.
Debug will get your attention, sooner or later Design How-To 6/17/2010 Post a comment Debug will get your attention one way or another. If you give it attention early in the development cycle, it will reduce the amount of time spent on debug later and in future designs as well as reducing the uncertainty related to debug.
Group aims to set standards for multicore tools News & Analysis 6/17/2010 Post a comment The Multicore Association has formed a new work group to tackle the problem of incompatible software development tools for multicore processors and expects to have a draft standard for one or more common data format and a Linux-based reference implementation of its work within a year.
Khronos upgrades parallel programming standard News & Analysis 6/15/2010 Post a comment The Khronos Group, an industry consortium focused on developing multimedia standards and application programming interfaces (APIs), has released version 1.1 of the OpenCL specification, a royalty-free standard for parallel programming of processors.
CEA-Leti, Docea team on next gen 3D-IC design News & Analysis 6/15/2010 Post a comment The Electronics and Information Technology Laboratory of the CEA (CEA-Leti) of France and Docea Power SAS (Moirans, France) announced they have sealed a laboratory agreement to combine their expertise in 3D silicon integration as well as thermal and low power design.
Altos expands corporate structure, global presence News & Analysis 6/15/2010 Post a comment Library characterization startup Altos Design Automation Inc. announced it has doubled headquarters space in Campbell, Calif., added John Ennis as worldwide vice president of sales and established presence in Beijing, China, to address customer demand and market potential.
TSMC, Tela trim logic die area by 15% News & Analysis 6/15/2010 Post a comment Taiwan Semiconductor Manufacturing Co. Ltd. has introduced its so-called Slim Library of standard cells, which reduces system-on-chip (SoC) routed logic block area by 15 percent compared to blocks routed through conventional standard cell libraries.
Reducing switching power with intelligent clock gating Design How-To 6/15/2010 3 comments Xilinx has introduced automated, fine-grain clock-gating solution that can reduce dynamic power by up to 30 percent for Virtex-6 and Spartan-6 FPGA designs. Intelligent clock-gating optimizations are automatically performed on the entire design, introduce no new tools or steps to the flow, and generate no changes to the existing logic or to the clocks that alter the behavior of the design. And, in most cases, the timing is also preserved.
Full Altera Stratix IV family in volume production News & Analysis 6/14/2010 Post a comment Programmable logic vendor Altera has commenced production shipments of the highest density member of its 40-nm Stratix IV FPGA family, the Stratix IV E EP4SE820. All members the Stratix IV family are now shipping in volume, according to the company.
EDA DesignLine's "what's new" list at DAC! Blog 6/11/2010 1 comment The countdown to the 47th Design Automation Conference (DAC) in Anaheim, Calif., has begun. Before you get to the Convention Center, have a look at EDA DesignLine's list of EDA products that will be introduced and showcased at the show.
Analysis: Acquisitions reflect broadening view of EDA News & Analysis 6/11/2010 2 comments Recent acquisition activity by large EDA vendors represents the most recent and perhaps boldest evidence of a broadening focus that steps away from a "myopic view of what EDA is that was killing the industry," according to a prominent EDA analyst.
Synopsys buys Synfora assets News & Analysis 6/10/2010 Post a comment In its second major acquisition announcement in one day, EDA and IP vendor Synopsys said it has acquired technology, engineering resources and other assets of high-level synthesis EDA vendor Synfora Inc. The financial terms of the deal, which closed Thursday, were not disclosed.
ARM shares spike again News & Analysis 6/10/2010 1 comment Shares in processor intellectual property licensor ARM Holdings plc spiked on Thursday taking the stock up above 300 pence a share from an opening price of 273.4 pence.
Time is right for clockless design Design How-To 6/10/2010 11 comments The demands of consumer applications to combine high performance with low power are forcing continued innovation in how the chips that power them are designed. After many years in the research labs, asynchronous technology has arrived as a viable approach, thanks to an emerging set of tools and capabilities from specialized suppliers who understand that the technology must not just work in concept, but also meet certain market requirements in order to be more broadly accepted and used.
Teklatech sets foot in Japan Product News 6/9/2010 Post a comment EDA startup Teklatech A/S (Copenhagen, Denmark) announced it has expanded its worldwide presence with the appointment of Japanese representation.
First MRAM-based FPGA taped-out Product News 6/9/2010 Post a comment Menta SAS and LIRMM have taped out what they describe as the of worlds first MRAM-based FPGA which has patent-protected circuitry enabling compact integration of MRAM and embedded-FPGA solutions.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments