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Content tagged with Design Tools (EDA)
posted in June 2010
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Module aids Camera Link FPGA image processing
Product News  
6/8/2010   Post a comment
National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing.
Actel bundles access to IP with Libero tools
News & Analysis  
6/8/2010   Post a comment
Actel is including free access to its IP libraries in its Libero Gold edition and RTL-source IP libraries in its Libero Platinum edition providing access to more than 50 IP cores.
PRODUCT HOW-TO: Verifying your Configurable OCP Interfaces
Design How-To  
6/7/2010   Post a comment
How to use Jasper Design Automation's configurable Open Core Protocol formal verification IP generator to automatically creating appropriate OCP properties for a specific design implementation and using it to develop a verification plan for OCP designs.
Altera sees Q2 sales at high end of guidance
News & Analysis  
6/7/2010   Post a comment
Programmable logic vendor Altera said it expects second quarter revenue to be up 10 to 12 percent compared with the first quarter, moving to the high end of its previously guided range after saying in April it expected second quarter revenue to be up by 8 to 12 percent.
Synopsys, IEEE push open source modeling standard
News & Analysis  
6/7/2010   1 comment
EDA and IP vendor Synopsys announced the open source availability of its Interconnect Technology Format for parasitic modeling and the formation of a technical advisory board under the auspices of IEEE Industry Standards and Technology Organization.
FPGA startup SiliconBlue snares $15M in funding
News & Analysis  
6/7/2010   Post a comment
Programmable logic startup SiliconBlue Technologies announced the closing of $15 million in Series C financing from a group of venture capital firms.
TSMC adds 3-D, ESL to platform efforts
News & Analysis  
6/7/2010   Post a comment
Silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has expanded its ''platform'' initiative in an effort to speed up new designs in the foundry market.
ST uses EVE's ZeBu emulator
Product News  
6/7/2010   Post a comment
European chipmaker STMicroelectronics NV (Geneva, Switzerland) announced it has licensed the ZeBu emulation system from EVE SA (Palaiseau, France).
Visible light illuminates a new approach for wireless comms
News & Analysis  
6/7/2010   4 comments
With preparations well under way for a societal shift to solid-state lighting based on high-output LEDs, a proverbial light bulb has appeared above the heads of some forward-looking engineers.
SOFTWARE/HARDWARE TOOLS - Experts to be challenged to create logic analyzer in a day
News & Analysis  
6/4/2010   Post a comment
“Logic Analyzer in a Day” will showcase experts' talent with Opal Kelly FPGA modules and FrontPanel SDK. The Logic Analyzers will be available, FREE, on the Opal Kelly website.
SOFTWARE TOOLS - MIPS Technologies and SySDSoft announce first LTE Protocol Stack on Android platform
News & Analysis  
6/4/2010   Post a comment
MIPS Technologies and SySDSoft announce first LTE Protocol Stack on Android platform, achieving Category 4 (CAT4) performance on MIPS-based chipset.
Altera could increase Q2 sales target
News & Analysis  
6/4/2010   Post a comment
Programmable logic vendor Altera will likely raise its sales target for the second quarter when the company issues a scheduled mid-quarter guidance update June 7, according to an analyst.
Xilinx to raise $520 million through bonds
News & Analysis  
6/3/2010   Post a comment
Programmable logic vendor Xilinx said it plans to offer $520 million worth of convertible senior notes which would be due in June 2017.
Join the Conversation: Do we need another Linux group?
News & Analysis  
6/3/2010   10 comments
Do we need another mobile Linux consortium? That's the question posed by the launch of Linaro, created by ARM, Freescale, IBM, Samsung, ST-Ericsson and Texas Instruments to develop Linux software for ARM-based SoCs. We'd like to hear what you think.
A look back at the last 10 years of chip design
Blog  
6/3/2010   Post a comment
The world of IC design looks very different than it did 10 years ago, when EVE incorporated and started building its first hardware emulator. In 2000, the semiconductor industry was still reveling in the new millennium and the economy was going strong.
DAC readies for managers, designers and 'social' tools
News & Analysis  
6/3/2010   Post a comment
The Design Automation Conference will have a brainstorming panel and presentations by management from leading-edge companies to highlight choices for flows, methodologies and suppliers.
French EDA firms team on power-aware platform
Product News  
6/3/2010   Post a comment
Ten days before the grand opening of the 47th DAC in Anaheim, Calif., Docea Power SAS (Moirans, France) and Paris-based Magillem SA said they are working on a power-aware platform description based on IEEE 1685IP-XACT.
TSMC uses SpringSoft's layout automation tool
News & Analysis  
6/3/2010   Post a comment
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) announced it has licensed the Laker custom layout automation system from SpringSoft Inc. for mixed-signal, memory and I/O design applications.
Design-for-power startup raises $1.5M
News & Analysis  
6/2/2010   Post a comment
Design-for-power startup company Docea Power SAS (Moirans, France) announced it has raised $1.5 million in an initial round of financing.
TSMC donates iDRC to Si2
News & Analysis  
6/2/2010   Post a comment
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) said it has donated iDRC, a vendor-neutral language for describing IC design rules, to the Silicon Integration Initiative (Si2).
Kilopass unveils programmable 4-Mb non-volatile IP
News & Analysis  
6/2/2010   Post a comment
Kilopass Technology unveiled a one-time programmable 4-Mb non-volatile memory IP product large enough to store the firmware and boot code that is traditionally stored in external serial-flash EEPROM chips.
A monitor-based approach to verification
Design How-To  
6/2/2010   Post a comment
A monitor-based verification approach is an efficient way to make many verification environment components reusable within the same project and to keep the environment more simple and similar across various levels.
SOFTWARE TOOLS - Docea adds power and thermal modeling and analysis to Aceplorer
News & Analysis  
6/1/2010   Post a comment
Docea Power's Aceplorer 2.0 adds project management capabilities to boost productivity, along with a link to virtual platforms to assess the impact of complex scenarios and embedded software on a system’s power consumption.
ST, NXP combine efforts on NFC API for Android
News & Analysis  
6/1/2010   Post a comment
ST, NXP, Trusted Logic and Stollmann have said they will promote a common hardware-independent application programming interface for near field communications on mobile phones running Android software.
CoFluent Studio adds embedded C code generation capability
Product News  
6/1/2010   Post a comment
At this year's DAC in Anaheim, from June 13 to June 18, French ESL company CoFluent Design (Nantes, France) said it will present a pre-release demonstration of the embedded C code generation feature in its CoFluent Studio ESL modeling and simulation software environment.
Imperas defines flow to run Mentor Nucleus RTOS, EDGE on OVP reference platforms
News & Analysis  
6/1/2010   Post a comment
Imperas Ltd. claimed it has conceived a flow that eases embedded software development with the Mentor Nucleus Real-Time Operating System (RTOS) and the Mentor Embedded software tools.
ASE uses Apache's chip-package-system analysis tools
Product News  
6/1/2010   Post a comment
Taiwan's Advanced Semiconductor Engineering (ASE) Inc. announced it has licensed Apache Design Solutions’ products for chip-package-system convergence.
Cadence uses Rapid Bridge's LiquidIP
Product News  
6/1/2010   Post a comment
Cadence Design Systems Inc. and Rapid Bridge LLC have signed an agreement under which Rapid Bridge's LiquidIP, a system of interdependent, silicon-proven IPs, becomes available as part of the Cadence Open Integration Platform.
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