Relaxed rules proposed for early 65-nm processes News & Analysis 7/25/2002 Post a comment Chip designers planning to scale their system-on-chip designs to the 65-nanometer process technology node by the middle of the decade were given fair warning at Semicon West this past week: Steering past delays in lithography, interconnects and other elements crucial to extending Moore's Law will require some tricky navigation.
Every new design is an ESD test chip Design How-To 7/18/2002 Post a comment The effect of low ESD immunity on a new product introduction can be both obvious and subtle. Manufacturing and test facilities adhere to ANSI standards for ESD protection and handling of chips based on minimum IC ESD immunity requirements.
Test flow speeds up MP3 decoder development to eight weeks Design How-To 7/18/2002 Post a comment In the SoC design and integration methodology of a MPEG1/2 Audio Layer 3 (MP3) decoder chip, a top-down integration flow, combined with a focus on constraint-driven timing analysis, modular simulation and DFT solutions, led to an implementation cycle of only eight weeks.
In Design Closure, Timing Isn't Everything Design How-To 7/15/2002 Post a comment While timing closure remains a key component of chip design, correct
timing is only one of several design parameters. TechOnLine's Jim
Lipman explains why he thinks EDA tool vendors need to put more effort
into developing high-level tools to help designers meet power and other design specifications.
VSIA guidelines assist SoC Signal Integrity News & Analysis 7/9/2002 Post a comment Authors and integrators of intellectual property (IP) are trying to tape out chips without real verification of chip-level signal integrity matters. EDA solutions are complex and inadequate, with capacity-limited extraction tools that run out of steam well before system-on-chip (SoC) design sizes are met.
OC-48 SONET receiver consumes significantly less logic in FPGA News & Analysis 7/1/2002 Post a comment n many Sonet processing applications, a commercial vendor application-specific IC (ASIC) or application-specific standard product (ASSP) implements basic Sonet functions such as framing and performance monitoring. Frequently, a field-programmable gate array (FPGA) is also required to interface to the ASIC and perform customer-specific functions.
FPGAs adapt security functions in security blade design News & Analysis 7/1/2002 Post a comment s networking makes greater strides, the need for security becomes increasingly paramount. However, even with rapid advances in networking technology, security lags behind and in most instances, is only assigned to virtual private networks (VPNs) and firewalls.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments