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Content tagged with Design Tools (EDA)
posted in July 2002
Relaxed rules proposed for early 65-nm processes
News & Analysis  
7/25/2002   Post a comment
Chip designers planning to scale their system-on-chip designs to the 65-nanometer process technology node by the middle of the decade were given fair warning at Semicon West this past week: Steering past delays in lithography, interconnects and other elements crucial to extending Moore's Law will require some tricky navigation.
Testable SoCs
News & Analysis  
7/18/2002   Post a comment
Design for testability: separating the myths from reality
Design How-To  
7/18/2002   Post a comment
The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT).
Every new design is an ESD test chip
Design How-To  
7/18/2002   Post a comment
The effect of low ESD immunity on a new product introduction can be both obvious and subtle. Manufacturing and test facilities adhere to ANSI standards for ESD protection and handling of chips based on minimum IC ESD immunity requirements.
Testing the HyperTransport PHY core
Design How-To  
7/18/2002   Post a comment
Achieving Gigabit data rates is a challenge that can excite the imagination of chip designers.
Test flow speeds up MP3 decoder development to eight weeks
Design How-To  
7/18/2002   Post a comment
In the SoC design and integration methodology of a MPEG1/2 Audio Layer 3 (MP3) decoder chip, a top-down integration flow, combined with a focus on constraint-driven timing analysis, modular simulation and DFT solutions, led to an implementation cycle of only eight weeks.
How systems level considerations impact cost-effective Gigabit Ethernet PHYs
Design How-To  
7/18/2002   Post a comment
The trigger that enabled the transition from Ethernet (10Mb) to Fast Ethernet (100Mb) throughout the data center and eventually to the desktop occurred when IT decision-makers could purchase "10x the performance for 2-3x the price".
SoC testability: Designers confront speed, complexity issues
Design How-To  
7/18/2002   Post a comment
For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem.
In Design Closure, Timing Isn't Everything
Design How-To  
7/15/2002   Post a comment
While timing closure remains a key component of chip design, correct timing is only one of several design parameters. TechOnLine's Jim Lipman explains why he thinks EDA tool vendors need to put more effort into developing high-level tools to help designers meet power and other design specifications.
Firmware-friendly reset design
News & Analysis  
7/12/2002   Post a comment
I/O buffer timing ensures board Signal Integrity
News & Analysis  
7/9/2002   Post a comment
As the speed of modern high-performance buses increases to 400 MHz and beyond, signal integrity concerns have a large and increasing effect on timing closure.
VSIA guidelines assist SoC Signal Integrity
News & Analysis  
7/9/2002   Post a comment
Authors and integrators of intellectual property (IP) are trying to tape out chips without real verification of chip-level signal integrity matters. EDA solutions are complex and inadequate, with capacity-limited extraction tools that run out of steam well before system-on-chip (SoC) design sizes are met.
OC-48 SONET receiver consumes significantly less logic in FPGA
News & Analysis  
7/1/2002   Post a comment
n many Sonet processing applications, a commercial vendor application-specific IC (ASIC) or application-specific standard product (ASSP) implements basic Sonet functions such as framing and performance monitoring. Frequently, a field-programmable gate array (FPGA) is also required to interface to the ASIC and perform customer-specific functions.
IP core implements flexible network services on FPGAs
News & Analysis  
7/1/2002   Post a comment
Next generation routers are providing solutions to service providers who need to introduce new revenue generating services while ensuring service quality.
FPGAs adapt security functions in security blade design
News & Analysis  
7/1/2002   Post a comment
s networking makes greater strides, the need for security becomes increasingly paramount. However, even with rapid advances in networking technology, security lags behind and in most instances, is only assigned to virtual private networks (VPNs) and firewalls.
FPGA/DSP blend tackles telecom apps
Design How-To  
7/1/2002   Post a comment
Implementing the digital signal processing (DSP) tasks in telecommunications applications typically requires chips with very strong number-crunching capabilities.
FPGA-based FFT engine handles four times more input data
Design How-To  
7/1/2002   Post a comment
For years, field-programmable gate array (FPGA) technology has been a major cornerstone of board-level product design for embedded software radio and communication systems.
Designing an FPGA-based network communications device
Design How-To  
7/1/2002   Post a comment
When our R&D team in Siemens Information and Communications Network Division set out to develop an advanced network communications device, the "ACE" (AAL2 Connecting Element), we faced serious challenges.
CPLDs become heart of scalable storage system
Design How-To  
7/1/2002   Post a comment
In early 2001, Nexsan Technologies began development on a new family of ATA RAID devices.
Building mesh-based distributed switch fabrics with programmable logic
Design How-To  
7/1/2002   Post a comment
Mesh networks can be used to build distributed switch fabrics.


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