Techniques for energy-efficient SoC design News & Analysis 7/24/2003 Post a comment System-on-chip designers have a new challenge: energy efficiency. In this tutorial, authors including National Semiconductors' David Tamura and Synopsys' Barry Pangrle and Rajiv Maheshwary present techniques such as dynamic and adaptive voltage and frequency scaling.
Startup rolls FPGA prototyping tool News & Analysis 7/21/2003 Post a comment FPGA tool startup Hier Design Inc. is launching a silicon virtual-prototyping tool that applies the advanced methodologies of the ASIC world to high-end field-programmable gate array designs, the company said.
Verifying PCI Express design IP Design How-To 7/18/2003 Post a comment The PCI Express standard is a new serial interconnect architecture that supports a range of devices for chip-to-chip, board-to-board and adapter interfaces used computing and communications applications.
Platform eases SoC IP Verification Design How-To 7/18/2003 Post a comment A typical SoC design requires IP procurement and development, complete system level verification and back-end design. Increasingly, SoC designers are emulating their design to perform functional validation to avoid expensive ASIC re-spins.
Verification of Third-Party CPU Intellectual Property Design How-To 7/18/2003 Post a comment The quality of pre-silicon verification is a primary criterion for the successful implementation of today's ASICs. Increasingly, high development costs and the pressure to get to market quickly leave little room for insufficient verification, which often leads to multiple silicon revisions.
Organized test code furthers firmware reuse Design How-To 7/18/2003 Post a comment Because of the high cost of chip fabrication, it is beneficial to find and fix bugs and design flaws during the design phase. But schedule constraints limit the amount of testing that can be performed at this stage.
Interface IP requires real-world validation Design How-To 7/18/2003 Post a comment he demand for outsourced semiconductor intellectual property (IP) has risen in recent years as chip designers strive to meet the challenging demands of smaller geometries and shorter product life cycles.
Mixed-Signal IC Layout Tools Support 'Touch and Feel' News & Analysis 7/11/2003 Post a comment Mentor Graphics is announcing a series of IC layout tools intended to complete the design flow for mixed-signal SoCs. Called ICassemble, the tool is designed to complement top-down, hierarchical mixed-signal design with a tool
that provides interactive floorplanning and routing.
Managing loss in high-speed PCBs News & Analysis 7/7/2003 Post a comment Signal loss is a serious problem facing high-speed PCB designers. In this tutorial, GigaTest Labs' Eric Bogatin and Mentor Graphics' Steve Kaufer show you when loss is important, what causes it, how it can be measured, and how it can be minimzed.
EDA revenues fell 6 percent in first quarter News & Analysis 7/7/2003 Post a comment The design automation industry's first-quarter 2003 revenues fell 6 percent from the year-ago quarter, according to the EDA Consortium's latest market statistics survey. But EDAC officials claimed the numbers may actually point to a recovery, since they show sequential growth over the fourth quarter of 2002.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments