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posted in July 2003
Philips Keeps Options Open After Selling Adelante's Design Tool
News & Analysis  
7/25/2003   Post a comment
Philips Semiconductor executives are downplaying speculation that it Adelante Technologies DSP core unit will be folded back into the parent company after selling the spin-off's key design tool technology to ARM Ltd.
Techniques for energy-efficient SoC design
News & Analysis  
7/24/2003   Post a comment
System-on-chip designers have a new challenge: energy efficiency. In this tutorial, authors including National Semiconductors' David Tamura and Synopsys' Barry Pangrle and Rajiv Maheshwary present techniques such as dynamic and adaptive voltage and frequency scaling.
ARM acquires design part of DSP firm Adelante
News & Analysis  
7/22/2003   Post a comment
RISC processor licensor ARM Holdings plc said Tuesday (July 22, 2003) it has purchased Adelante Technologies Belgium, a part of Adelante Technologies Holding B.V.
Startup rolls FPGA prototyping tool
News & Analysis  
7/21/2003   Post a comment
FPGA tool startup Hier Design Inc. is launching a silicon virtual-prototyping tool that applies the advanced methodologies of the ASIC world to high-end field-programmable gate array designs, the company said.
Verifying PCI Express design IP
Design How-To  
7/18/2003   Post a comment
The PCI Express standard is a new serial interconnect architecture that supports a range of devices for chip-to-chip, board-to-board and adapter interfaces used computing and communications applications.
Automated verification of configurable IP blocks
Design How-To  
7/18/2003   Post a comment
o efficiently and profitably exploit millions of available SoC gates, companies must acquire pre-verified IP blocks in the same way they now buy pre-tested chips.
Verification IP adapts to SoC complexity
Design How-To  
7/18/2003   Post a comment
The time-proven methodology of writing directed tests to meet coverage goals is no longer a viable methodology because the verification task has grown exponentially.
Verification in the CoreWare suite
Design How-To  
7/18/2003   Post a comment
Today's market conditions require that IP developers provide high quality IP that is easily reusable by the system integrator, or they face extinction.
Handling multi-sourced IP in system
Design How-To  
7/18/2003   Post a comment
Using embedded silicon intellectual property (IP) from multiple sources has become common in system-on-chip (SoC) designs.
Platform eases SoC IP Verification
Design How-To  
7/18/2003   Post a comment
A typical SoC design requires IP procurement and development, complete system level verification and back-end design. Increasingly, SoC designers are emulating their design to perform functional validation to avoid expensive ASIC re-spins.
Verification of Third-Party CPU Intellectual Property
Design How-To  
7/18/2003   Post a comment
The quality of pre-silicon verification is a primary criterion for the successful implementation of today's ASICs. Increasingly, high development costs and the pressure to get to market quickly leave little room for insufficient verification, which often leads to multiple silicon revisions.
Organized test code furthers firmware reuse
Design How-To  
7/18/2003   Post a comment
Because of the high cost of chip fabrication, it is beneficial to find and fix bugs and design flaws during the design phase. But schedule constraints limit the amount of testing that can be performed at this stage.
Interface IP requires real-world validation
Design How-To  
7/18/2003   Post a comment
he demand for outsourced semiconductor intellectual property (IP) has risen in recent years as chip designers strive to meet the challenging demands of smaller geometries and shorter product life cycles.
IP quality requires verification focus
Design How-To  
7/18/2003   Post a comment
When a system-on-chip project team considers using intellectual property, one of the hardest problems is assessing the quality of the available options.
Hierarchical design methodology supports complex FPGAs
Design How-To  
7/17/2003   Post a comment
An ASIC-style design methodology is needed to support complex FPGAs, says Salil Raje, CTO of EDA startup Hier Design. In this article, Raje walks you through a methodology that reduces iterations and improves utilization and device performance.
Phase noise and jitter -- a primer for digital designers
Design How-To  
7/14/2003   Post a comment
Whether you're designing chips or boards, you need to understand phase noise and jitter if you're working with high-speed design. In this tutorial, Neil Roberts, analog designer at Zarlink Semiconductor, explains what digital designers need to know.
Mixed-Signal IC Layout Tools Support 'Touch and Feel'
News & Analysis  
7/11/2003   Post a comment
Mentor Graphics is announcing a series of IC layout tools intended to complete the design flow for mixed-signal SoCs. Called ICassemble, the tool is designed to complement top-down, hierarchical mixed-signal design with a tool that provides interactive floorplanning and routing.
Managing loss in high-speed PCBs
News & Analysis  
7/7/2003   Post a comment
Signal loss is a serious problem facing high-speed PCB designers. In this tutorial, GigaTest Labs' Eric Bogatin and Mentor Graphics' Steve Kaufer show you when loss is important, what causes it, how it can be measured, and how it can be minimzed.
EDA revenues fell 6 percent in first quarter
News & Analysis  
7/7/2003   Post a comment
The design automation industry's first-quarter 2003 revenues fell 6 percent from the year-ago quarter, according to the EDA Consortium's latest market statistics survey. But EDAC officials claimed the numbers may actually point to a recovery, since they show sequential growth over the fourth quarter of 2002.
Hardware-software codesign used in STMicro ADSL chip
News & Analysis  
7/7/2003   Post a comment
Target Compiler Technologies NV, which has been developing high-level DSP hardware-software co-design tools since 1996, has persuaded STMicroelectronics to design its next generation ADSL chip using Chess/Checkers tool suite.

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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