Embedded Systems Conference
Breaking News
Content tagged with Design Tools (EDA)
posted in July 2003
Philips Keeps Options Open After Selling Adelante's Design Tool
News & Analysis  
7/25/2003   Post a comment
Philips Semiconductor executives are downplaying speculation that it Adelante Technologies DSP core unit will be folded back into the parent company after selling the spin-off's key design tool technology to ARM Ltd.
Techniques for energy-efficient SoC design
News & Analysis  
7/24/2003   Post a comment
System-on-chip designers have a new challenge: energy efficiency. In this tutorial, authors including National Semiconductors' David Tamura and Synopsys' Barry Pangrle and Rajiv Maheshwary present techniques such as dynamic and adaptive voltage and frequency scaling.
ARM acquires design part of DSP firm Adelante
News & Analysis  
7/22/2003   Post a comment
RISC processor licensor ARM Holdings plc said Tuesday (July 22, 2003) it has purchased Adelante Technologies Belgium, a part of Adelante Technologies Holding B.V.
Startup rolls FPGA prototyping tool
News & Analysis  
7/21/2003   Post a comment
FPGA tool startup Hier Design Inc. is launching a silicon virtual-prototyping tool that applies the advanced methodologies of the ASIC world to high-end field-programmable gate array designs, the company said.
Verifying PCI Express design IP
Design How-To  
7/18/2003   Post a comment
The PCI Express standard is a new serial interconnect architecture that supports a range of devices for chip-to-chip, board-to-board and adapter interfaces used computing and communications applications.
Automated verification of configurable IP blocks
Design How-To  
7/18/2003   Post a comment
o efficiently and profitably exploit millions of available SoC gates, companies must acquire pre-verified IP blocks in the same way they now buy pre-tested chips.
Verification IP adapts to SoC complexity
Design How-To  
7/18/2003   Post a comment
The time-proven methodology of writing directed tests to meet coverage goals is no longer a viable methodology because the verification task has grown exponentially.
Verification in the CoreWare suite
Design How-To  
7/18/2003   Post a comment
Today's market conditions require that IP developers provide high quality IP that is easily reusable by the system integrator, or they face extinction.
Handling multi-sourced IP in system
Design How-To  
7/18/2003   Post a comment
Using embedded silicon intellectual property (IP) from multiple sources has become common in system-on-chip (SoC) designs.
Platform eases SoC IP Verification
Design How-To  
7/18/2003   Post a comment
A typical SoC design requires IP procurement and development, complete system level verification and back-end design. Increasingly, SoC designers are emulating their design to perform functional validation to avoid expensive ASIC re-spins.
Verification of Third-Party CPU Intellectual Property
Design How-To  
7/18/2003   Post a comment
The quality of pre-silicon verification is a primary criterion for the successful implementation of today's ASICs. Increasingly, high development costs and the pressure to get to market quickly leave little room for insufficient verification, which often leads to multiple silicon revisions.
Organized test code furthers firmware reuse
Design How-To  
7/18/2003   Post a comment
Because of the high cost of chip fabrication, it is beneficial to find and fix bugs and design flaws during the design phase. But schedule constraints limit the amount of testing that can be performed at this stage.
Interface IP requires real-world validation
Design How-To  
7/18/2003   Post a comment
he demand for outsourced semiconductor intellectual property (IP) has risen in recent years as chip designers strive to meet the challenging demands of smaller geometries and shorter product life cycles.
IP quality requires verification focus
Design How-To  
7/18/2003   Post a comment
When a system-on-chip project team considers using intellectual property, one of the hardest problems is assessing the quality of the available options.
Hierarchical design methodology supports complex FPGAs
Design How-To  
7/17/2003   Post a comment
An ASIC-style design methodology is needed to support complex FPGAs, says Salil Raje, CTO of EDA startup Hier Design. In this article, Raje walks you through a methodology that reduces iterations and improves utilization and device performance.
Phase noise and jitter -- a primer for digital designers
Design How-To  
7/14/2003   Post a comment
Whether you're designing chips or boards, you need to understand phase noise and jitter if you're working with high-speed design. In this tutorial, Neil Roberts, analog designer at Zarlink Semiconductor, explains what digital designers need to know.
Mixed-Signal IC Layout Tools Support 'Touch and Feel'
News & Analysis  
7/11/2003   Post a comment
Mentor Graphics is announcing a series of IC layout tools intended to complete the design flow for mixed-signal SoCs. Called ICassemble, the tool is designed to complement top-down, hierarchical mixed-signal design with a tool that provides interactive floorplanning and routing.
EDA revenues fell 6 percent in first quarter
News & Analysis  
7/7/2003   Post a comment
The design automation industry's first-quarter 2003 revenues fell 6 percent from the year-ago quarter, according to the EDA Consortium's latest market statistics survey. But EDAC officials claimed the numbers may actually point to a recovery, since they show sequential growth over the fourth quarter of 2002.
Managing loss in high-speed PCBs
News & Analysis  
7/7/2003   Post a comment
Signal loss is a serious problem facing high-speed PCB designers. In this tutorial, GigaTest Labs' Eric Bogatin and Mentor Graphics' Steve Kaufer show you when loss is important, what causes it, how it can be measured, and how it can be minimzed.
Hardware-software codesign used in STMicro ADSL chip
News & Analysis  
7/7/2003   Post a comment
Target Compiler Technologies NV, which has been developing high-level DSP hardware-software co-design tools since 1996, has persuaded STMicroelectronics to design its next generation ADSL chip using Chess/Checkers tool suite.

Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

March 28 is Arduino Day -- Break Out the Party Hats!
Max Maxfield
Well, here's a bit of a conundrum. I just received an email from my chum David Ashton who hails from the "Unfinished Continent" Down Under. David's message was short and sweet; all he said ...

Bernard Cole

A Book For All Reasons
Bernard Cole
1 Comment
Robert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...

Martin Rowe

Leonard Nimoy, We'll Miss you
Martin Rowe
Like many of you, I was saddened to hear the news of Leonard Nimoy's death. His Star Trek character Mr. Spock was an inspiration to many of us who entered technical fields.

Rich Quinnell

Making the Grade in Industrial Design
Rich Quinnell
As every developer knows, there are the paper specifications for a product design, and then there are the real requirements. The paper specs are dry, bland, and rigidly numeric, making ...

Special Video Section
After a four-year absence, Infineon returns to Mobile World ...
A laptop’s 65-watt adapter can be made 6 times smaller and ...
An industry network should have device and data security at ...
The LTC2975 is a four-channel PMBus Power System Manager ...
In this video, a new high speed CMOS output comparator ...
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...
General-purpose DACs have applications in instrumentation, ...
Linear Technology demonstrates its latest measurement ...
Demos from Maxim Integrated at Electronica 2014 show ...
Bosch CEO Stefan Finkbeiner shows off latest combo and ...
STMicroelectronics demoed this simple gesture control ...
Keysight shows you what signals lurk in real-time at 510MHz ...
TE Connectivity's clear-plastic, full-size model car shows ...
Why culture makes Linear Tech a winner.
Recently formed Architects of Modern Power consortium ...
Specially modified Corvette C7 Stingray responds to ex Indy ...
Avago’s ACPL-K30T is the first solid-state driver qualified ...
NXP launches its line of multi-gate, multifunction, ...
EE Times Senior Technical Editor Martin Rowe will interview EMC engineer Kenneth Wyatt.
Flash Poll