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Content tagged with Design Tools (EDA)
posted in July 2004
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PCI Express made easy
Design How-To  
7/30/2004   Post a comment
Looking for an easy way to implement PCI Express on chip? Companies including Cascade, Denali and Knowlent have the IP you need to do it.
Using formal verification to create robust IP
News & Analysis  
7/30/2004   Post a comment
Traditional silicon IP verification methods leave much to be desired. Real Intent's Jay Littlefield (right) shows how to use formal methods, including assertions in both simulation and formal verification, to provide a more thorough solution.
Nassda hit with second class-action suit in a day
News & Analysis  
7/30/2004   Post a comment
The lawsuits just keep coming for simulation tool vendor Nassda Corp.
Accellera approves Property Specification Language
News & Analysis  
7/29/2004   Post a comment
Providing an alternative to proprietary assertion languages, the Accellera standards organization has approved the Property Specification Language (PSL) version 1.1 and has begun the process of IEEE standardization, said Accellera chairman Dennis Brophy (right).
Nassda faces investor lawsuit
News & Analysis  
7/29/2004   Post a comment
The legal woes of circuit simulation provider Nassda Corp.'s deepened on Thursday (July 29) as the noted class-action law firm Lerach Coughlin Stoia & Robbins filed a complaint on behalf of Nassda shareholders.
Conferees ponder Taiwan's design rise
News & Analysis  
7/29/2004   Post a comment
Taiwan's ascendancy in the electronics design food chain seemed official on the floors of the fourth annual Embedded System Conference-Asia and the twelfth annual Electronics Design Automation & Test-Taiwan Conference & Exhibition here this week. From Hsinchu, Majeed Ahmad filed this report.
Améliorer la convergence de timing avec la synthèse physique
News & Analysis  
7/29/2004   Post a comment
Les concepteurs sont témoins des changements radicaux intervenus dans le domaine de la synthèse logique des circuits intégrés et de la prise en compte du timing. Cette vague de changements prend sa source dans l’augmentation de la taille et de la complexité des circuits, mais surtout dans le besoin de considérer bien davantage les interconnexions à travers la synthèse physique.
Former Aptix CEO indicted for plot to kill judge
News & Analysis  
7/28/2004   1 comment
Former Aptix founder and CEO Amr Mohsen's legal troubles have escalated following a July 27 superseding indictment that states Mohsen attempted to have witnesses intimidated and a federal judge killed. Mohsen has been jailed since March as he apparently tried to flee the country prior to a perjury trial.
AWR, TSMC collaborate on design platform for SiGe RFICs
News & Analysis  
7/26/2004   Post a comment
Applied Wave Research (AWR) has teamed with foundry TSMC to develop a design platform for RFICs that will work on the Taiwanese group's 0.35 micron SiGe process. From London, John Walko reports.
Les bénéfices trimestriels de Xilinx chutent de 27%
News & Analysis  
7/23/2004   Post a comment
Le fabricant de FPGA, Xilinx Inc., a publié jeudi (22 juillet 2004) des recettes de 424 millions de dollars pour le premier trimestre de l’exercice 2005, soit une hausse de 5% par rapport au trimestre précédent et une hausse de 35% par rapport à la même période de l’année passée.
IP sale helps Cadence meet Q2 revenues
News & Analysis  
7/22/2004   Post a comment
Thanks in part to a sale of serial intellectual property (IP) to Rambus, Cadence Design Systems met Wall Street quarterly projections and swung to profitability in the second quarter of 2004. Analysts expressed some unease about the sale, but Mike Fister, Cadence's new CEO, said he was "very pleased" with the quarterly results.
A scalable approach to speeding physical verification
News & Analysis  
7/21/2004   Post a comment
Both distributed processing and multi-threading can speed physical verification, but the combination of the two is even better, says Synopsys authors including Rahul Kapoor (right). They use real-world examples to show how you can create a "scalable" verification strategy.
Put some OOP into your HDL
News & Analysis  
7/21/2004   Post a comment
It's time for hardware engineers to learn the benefits of object-oriented programming (OOP), says consultant Ronald Goodstein. Here's how it can help with maintainability and design reuse.
Mentor tool links FPGA, pcb design
News & Analysis  
7/20/2004   Post a comment
Mentor Graphics Corp. will roll out a tool this week that it says will enable concurrent FPGA and board design.
Summit seeks new CEO in advance of IPO
News & Analysis  
7/19/2004   Post a comment
Summit Design Inc., profitable since the beginning of 2003 and having tripled revenues since 2002, now wants to find a U.S.-based CEO with IPO experience to take the company public "as soon as the market's right".
Mentor tool links FPGA, pcb design
News & Analysis  
7/19/2004   Post a comment
Mentor Graphics Corp. will roll out a tool this week that it says will enable concurrent FPGA and board design. I/O Designer lets those designing printed-circuit boards graphically assign signals to FPGA pins, while observing the constraints set by FPGA device vendors, the company said.
Lattice upgrades PLD tool suite
News & Analysis  
7/19/2004   Post a comment
Lattice Semiconductor Corp. has released a new version of its ispLEVER programmable logic tool suite with support for new device families.
Poor FPGA packaging causes PCB problems
News & Analysis  
7/19/2004   Post a comment
FPGA packages are poorly designed with minimal testing. As a result, unwanted inductance can cause Vcc and ground bounce.
Synopsys-Chef kritisiert Chipindustrie
Product News  
7/19/2004   Post a comment
Herbe Kritik mussten sich die Vetreter der Chipindustrie auf der Semicon West anhören: Synopsys-Chef Aart de Geus, ein anerkannter EDA-Guru, forderte die Chiphersteller zu einer aktiveren Unterstützung des 'Design-for-Manufacturing'-Konzepts auf. Die Erarbeitung dieses Konzepts sei keine Einbahnstraße, mahnte de Geus: Beide Industrien müssten hier tätig werden.
Going virtual speeds SoCs
News & Analysis  
7/19/2004   Post a comment
An ongoing collaboration between Synopsys and Virtio promises the development of "virtual platforms" that can allow SoC software development to begin earlier.
Optimize drive strengths to reduce power problems
News & Analysis  
7/19/2004   Post a comment
To meet timing, most standard cells are over-driven, says Prolific's Dan Nenni. To reduce power consumption, over-driven paths must be minimized.
Connectivity engine speeds, streamlines microwave design
Product News  
7/16/2004   Post a comment
Agilent Technologies announced the industry's first physical connectivity engine to incorporate electrical connectivity built into layout artwork. The new engine for Agilent's Advanced Design System 2004A electronic design automation software helps speed and streamline microwave design for wireless communications products.
Cadence links acceleration to SystemC
News & Analysis  
7/15/2004   Post a comment
Enhancing the transaction-based capabilities of its Palladium emulation system, Cadence Design Systems has linked that platform to the Incisive unified simulator. This connection lets users run acceleration and emulation using SystemC testbenches.
Minimize IC power without sacrificing performance
News & Analysis  
7/15/2004   Post a comment
Power minimization techniques affect performance, says Cadence Design Systems' Anand Krishnamoorthy (right). In this tutorial, he describes the sources of IC power dissipation, presents a number of techniques for minimizing power, and discusses their impacts on timing closure.
Legal costs cloud Nassda revenue gains
News & Analysis  
7/14/2004   Post a comment
EDA provider Nassda reported record revenue for its third fiscal quarter ending June 30, 2004, but legal fees from an ongoing lawsuit from Synopsys are continuing to eat away at the company's bottom line. Nassda reported $11 million in revenue, a 46 percent year-to-year increase, but spent $2.7 million on legal fees during the quarter.
Express Logic ThreadX RTOS supports ARC cores
Product News  
7/14/2004   Post a comment
ARC International (San Jose, Calif.) has teamed-up with Express Logic, Inc. (San Diego) and will provide ARC customers with Express Logic's ThreadX RTOS support for the ARC 600 and ARC 700 configurable processor cores, as well as the ARCtangent cores. Developers can now use ThreadX to run embedded applications on a wider range of ARC's configurable cores.
Power-Management mal ganz anders
News & Analysis  
7/14/2004   Post a comment
Mit zunehmendem Interesse für Low-Power-Designs im Bereich von 130 Nanometer und darunter tritt das Problem von Sub-Threshold-Leckströmen immer deutlicher zu Tage. Ein kalifornisches Unternehmen hat einen neuen Ansatz entwickelt, die unerwünschten Ströme unter Kontrolle zu bringen.
Aldec promises 'affordable' acceleration
News & Analysis  
7/14/2004   Post a comment
Promising to provide an "affordable" option for RTL debugging and verification, Aldec Inc. is announcing Riviera-IPT Desktop, an FPGA-based acceleration solution that can be leased for less than $25,000 per year.
Vicor launches web-based technical library
Product News  
7/13/2004   Post a comment
Vicor Corporation's new Technical Library, a component of the company's web site, offers engineers a broad knowledge database, from the basics of designing with component modules to information about the differences between the Intermediate Bus Architecture (IBA) and Factorized Power Architecture (FPA). The site provides "one-click" access to Vicor's interactive design tools and design calculators, as well as applications manuals, mechanical drawings, and quality and certification information. U
Consultant creates low-end mixed-signal simulator
News & Analysis  
7/12/2004   Post a comment
In the middle of a tough design project in 2002, consultant Brendan Graham needed an inexpensive mixed-signal simulation tool. He couldn't find one, so his company, μSysIntegral, with financial backing from the client, built its own. Richard Goering reports.
Consultant creates low-end mixed-signal simulator
News & Analysis  
7/12/2004   Post a comment
In the middle of a tough design project in 2002, consultant Brendan Graham (right) needed an inexpensive mixed-signal simulation tool. He couldn't find one, so his company, µSysIntegral, with financial backing from the client, built its own.
CoWare adds MIPS models to SystemC library
News & Analysis  
7/12/2004   Post a comment
MPU core vendor MIPS Technology and CoWare Inc. have announced they have added SystemC-based processor support packages to CoWare's ConvergenSC Model Library.
New strategies shorten IP verification process
News & Analysis  
7/12/2004   Post a comment
To come up with a good topic for this In Focus report, I went down to the pond a mile behind my house, threw sticks in the water for my hound dogs to retrieve and engaged in some internal Socratic dialogue.
Specs eye functional verification, quality
News & Analysis  
7/12/2004   Post a comment
Business drivers, such as improved time-to-market and better resource utilization, are factoring ever more into the system-on-chip development process. One widely accepted method to meet those goals is design reuse.
Verifying SoCs and IP in parallel
News & Analysis  
7/12/2004   Post a comment
We all know that verifying a system-on-chip design can take up to 70 percent of the overall design cycle, and in even the most basic environment there are many considerations to weigh.
In-circuit SoC verification controls costs
News & Analysis  
7/12/2004   Post a comment
Both of the key benefits of a system-on-chip are related to cost. The first involves manufacturing. An SoC integrates many board components onto a single chip, which lowers the overall bill of materials.
Delivering verified AMBA AXI systems-on-chips
News & Analysis  
7/12/2004   Post a comment
The new Amba Advanced eXtensible Interface (AXI) is the next-generation Amba interface developed by ARM and targeted at high-performance, high-frequency system-on-chip designs.
From The Outside In Making Third-Party IP Work in Semiconductor Design
News & Analysis  
7/12/2004   Post a comment
More than 30 years after it first emerged as a technology, third-party intellectual property remains a significant source of delay and failure in semiconductor design.
Best Practices for a Reusable Verification Environment
News & Analysis  
7/12/2004   Post a comment
Verification reuse is critical to the productivity and efficiency of system-on-chip (SoC) verification. The foundation of this technique is well-designed verification codes and components that implement reusability techniques.
Platform-Based Design and Verification with Automated IP Integration
News & Analysis  
7/12/2004   Post a comment
System-on-chip (SoC) platforms provide an opportunity to resolve the productivity and verification challenges inherent in SoC creation. In earlier approaches, platform-based design required a substantial amount of work to transform an assortment of intellectual property (IP) into a specific design — including the resource-intensive and time-consuming tasks of setting up the tools and testbenches required to configure, verify and optimize the design.
Verification IP for IP verification
News & Analysis  
7/12/2004   Post a comment
The intellectual-property market is still in its infancy in terms of pricing, packaging, quality and integration standards, but IP solutions for standards-based interfaces are maturing quickly. One reason for this is simply the existence of a viable market for third-party IP vendors.
Vendor Cooperation Necessary for Successful IP Implementation
News & Analysis  
7/12/2004   Post a comment
The technical requirements for successfully implementing a complex standards-based silicon intellectual-property (IP) core in an electronic design automation tool flow are difficult.
IP Verification
News & Analysis  
7/12/2004   Post a comment
IP Verification
RF EDA moves from niche to mainstream
News & Analysis  
7/9/2004   Post a comment
Despite the recent semiconductor downturn, the RF EDA market is headed for explosive growth, says Applied Wave Research CEO James Spoto. In this column, he outlines the drivers for that growth.
How to choose a verification methodology
News & Analysis  
7/9/2004   Post a comment
So many functional verification tools, techniques, languages — how do you choose? In this tutorial, Cypress engineer Sri Purisai (right) examines various static and dynamic approaches, and presents an approach for choosing the right ones.
MoSys drops suit to force Synopsys merger
News & Analysis  
7/9/2004   Post a comment
After three days of trial, attorneys from Synopsys and Monolithic System Technology (MoSys) decided they'd had enough — so they agreed Thursday night (July 8) to settle the lawsuit that MoSys had filed in an attempt to force a merger between the companies. The companies go their own ways without any further liability or payment.
AutoVue adds PCB manufacturability analysis
News & Analysis  
7/8/2004   Post a comment
Cimmetry Systems' AutoVue, a visualization and collaboration tool for the engineering, architectural, and mechanical marketplaces, is extending its reach into EDA by adding new PCB design features. Among them is an ability to verify designs for manufacturing.
Software aids A/D converter performance modeling
News & Analysis  
7/7/2004   Post a comment
Converter modeling has often been overlooked, omitted, or done using an ideal data converter model. With more and more systems using mixed signal technology, the importance of system modeling is ever increasing. This, coupled with shortened design cycles and pressure for first pass success, drives the continuing importance of complete system modeling. Analog Devices' engineers describe a simulation program that may provide an answer this need.
Mentor announces support for SMIC mixed-signal process
News & Analysis  
7/7/2004   Post a comment
Mentor Graphics Corp. has been supplying a technology design kit for the 0.18-micron mixed signal manufacturing process technology offered by China's Semiconductor Manufacturing International Corp.
Page 1 / 2   >   >>


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