Topology Planning and Routing Design How-To 7/30/2007 Post a comment This article focuses on the PCB designer collaboration of the IP and further employing Topology Planning and Topology Routing tools to support the IP and complete the PCB design.
Simulator targets SoCs for handheld devices Product News 7/30/2007 Post a comment A simulator developed by the University of Southampton whose roots go back to research collaboration with another U.K. University, Newcastle, into developing interconnection technologies for multiprocessor SoCs, has been made available for download and is said to pave the way for more competitive handheld computing devices.
IP/foundry ecosystem facilitates 45-nm process design News & Analysis 7/26/2007 Post a comment To overcome 45-nm process challenges, semiconductor intellectual property (IP) providers and foundries are collaborating to provide designers with a combination of design resources and manufacturing expertise focused on advanced process nodes.
Dollar's weakness impacts ARM's revenues, profits News & Analysis 7/26/2007 Post a comment ARM Holdings plc has managed to grow dollar revenues by 11 percent in the first half to $258.4 million in what the company describes as "a challenging industry backdrop" and said it is on track to achieve full year estimates provided the dollar/sterling exchange does not change significantly.
The word is MAD Blog 7/24/2007 Post a comment Engineers must always be aware that what they design must be manufactured in a cost sensitive manner.
Mentor donates $20M in tools to Indian design center News & Analysis 7/24/2007 Post a comment Citing India's rise as "a powerhouse for the world's electronics industry," in the words of a Mentor executive, Mentor Graphics is donating a complete suite of EDA tools for classroom instruction and academic research to the RV-VLSI Design Center in Bengaluru.
Rethinking the System Design Process Design How-To 7/23/2007 2 comments System level modeling is evolving to solve how to determine quickly and efficiently how a change to a design specification might impact the performance of a proposed system.
Draft spec helps high-speed designs fly News & Analysis 7/19/2007 Post a comment The I/O Buffer Information Specification standards group is moving forward with a draft specification called Bird aimed at solving one of the thorniest problems in signal integrity today—accurately modeling interconnects at 5 Gbits/second and higher.
One Stop Shop Blog 7/17/2007 Post a comment The three leading EDA vendors have made acquisitions since the close of DAC to better serve their leading edge IC design customers.
Abstraction Levels and Hardware Design Design How-To 7/17/2007 1 comment The paper defines five levels of abstraction that are appropriate for hardware design. The register-transfer and behavioral levels are common terms without standard definitions. Here we give a definition, and also define three levels above what is commonly accepted as the behavioral level. The paper shows an example at each level and shows some high-level synthesis and simulation results illustrating some of the advantages of design at higher levels of abstraction.
Getting Back to Basics with Planning, Metrics, and Management Design How-To 7/13/2007 Post a comment This article is the first of a three part series focusing on how the new field of metric-driven engineering will improve design and verification processes. The next two installments will take a closer look at metric-driven engineering from a team leader and user's point of view.
Xilinx delivers ISE WebPACK 9.2i Product News 7/10/2007 1 comment ISE WebPACK 9.2i from Xilinx offers expanded support for latest 65nm Virtex-5 FPGAs; free, downloadable design solution now offers Microsoft Windows Vista Support.
Low Power Design Specification from RTL through GDSII Design How-To 7/9/2007 Post a comment Accellera, at the request and assistance of end users and with technical donations and contributions from multiple EDA vendors, developed the Unified Power Format (UPF) to capture low power design intent in a portable and interoperable form that can be used with most design verification and implementation tools throughout the design flow.
The EDA Dozen Blog 7/9/2007 Post a comment There are a dozen EDA companies among the 60 recognized by EE Times as the emerging companies in 2007.
Green Hills expands product suite to support Freescale's i.MX27 Product News 7/2/2007 Post a comment Green Hills Software Inc, announced that its product suite, including the MULTI integrated development environment, µ-velOSity royalty-free RTOS, TimeMachine tool suite, Green Hills compilers, and Green Hills Probe are now available for the Freescale i.MX27 multimedia applications processor.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments