Video: EDA eyes new opportunities for growth News & Analysis 7/31/2009 Post a comment Opportunities for EDA to generate more revenue from outside the semiconductor industry frequently surfaced in discussion at this year's Design Automation Conference, with executives suggesting that EDA could play in markets including medical devices, military/aerospace, automotive and clean energy technology.
Asyst sells assets to three companies News & Analysis 7/30/2009 Post a comment Ending perhaps the last chapter in a painful saga, Asyst Technologies Inc. has agreed to sell its entire assets to three companies: Crossing Automation Inc., Murata Machinery Ltd. and the Peer Group.
DAC attendance spots recessionary times News & Analysis 7/30/2009 Post a comment Preliminary attendace figures at this year's Design Automation Conference show an increase in total conference and exhibit attendance by 12 percent over last year's DAC held in Anaheim, Calif. and by three percent over the 2007 San Diego event.
GlobalFoundries could be the elusive Eurofoundry, and more News & Analysis 7/30/2009 1 comment If Infineon could be persuaded to follow ST and switch outsourced IC manufacturing to GlobalFoundries in Dresden, we would some of the way along the path to creating a Eurofoundry that would keep advanced digital CMOS manufacturing in Europe, albeit with the help of Abu-Dhabian petrodollars.
Micronova shrinks HiL simulator to desktop size Product News 7/30/2009 Post a comment With the NovaSim Micro, test devices vendor Micronova (Vierkirchen, Germany) has shrunk Hardware-in-the-loop (HiL) simulators to desktop size. Despite its small size, the simulator runs function tests on complex ECUs, the vendor promises.
Nvidia chief scientist to EDA: Give us power tools News & Analysis 7/30/2009 Post a comment Nvidia's chief scientist told the EDA community that chip designers need new tools to usher in a new era of computing, moving to "throughput computing" from an era of "denial architecture" that has seen the semiconductor industry squeeze more performance out of single-thread processors thanks to software.
ESL/HLS buzz at DAC Programmable Logic DesignLine Blog 7/30/2009 1 comment The buzz over electronic-system level design and high-level synthesis seems to have reached a new level at this year's Design Automation Conference.
Panel: Future job prospects bright for EDA pros News & Analysis 7/29/2009 Post a comment Amid concerns that EDA may be permanently shrinking, technical professionals with EDA experience nevertheless have good future job prospects, according to members of a career-oriented panel discussion at the Design Automation Conference.
DFM debated as a 'weapon of mass design' News & Analysis 7/29/2009 Post a comment The more than abused DFM acronym reared its ugly head again at a leading design engineering forum. The consensus is that Design for Manufacturing has its place in the chip design world, but basically it's a crapshoot.
TSMC keynoter touts cooperative business models News & Analysis 7/29/2009 Post a comment Future growth in EDA and other segments of the semiconductor industry supply chain depends on the evolution of a new breed of collaborative business model that enable partners to pool costs and increase profits, according to Fu-Chieh Hsu, vice president of Design & Technology Platform at TSMC.
The TSMC Tsunami at DAC 2009 Blog 7/28/2009 Post a comment In a well-orchestrated and clearly scripted show of force, the CEOs of the three "largest" companies in EDA appeared together under the Big Top at the 2009 Design Automation Conference in San Francisco on Monday, July 27th, for a highly touted afternoon keynote panel purportedly addressing "Futures for EDA."
ST uses Cadence signoff suite for 65- to 32nm design News & Analysis 7/28/2009 Post a comment European chipmaker STMicroelectronics NV said it has selected integration signoff solutions from Cadence Design Systems, Inc., including QRC Extraction and Encounter Timing System, for 65- to 32-nm design. It is qualifying the system for 32-nm process technologies.
EDA chiefs debate getting bigger slice of the pie News & Analysis 7/28/2009 Post a comment The age-old question of whether EDA gets its fair share of semiconductor ecosystem revenue reared its head at a panel discussion involving the CEOs of EDA's three largest companies at the Design Automation Conference, with at least one suggesting that the current recession may be the catalyst for a favorable change.
TU Dresden brings power efficient MPSoC to DAC News & Analysis 7/27/2009 Post a comment At the Design Automation Conference (DAC) that currently takes place in San Francisco, a group of researchers and chip designers from the Dresden Technical University present what they hope it could offer a solution for the challenge of modem signal processing for upcoming wireless communications generations.
FPGA startups stare down giants and ghosts News & Analysis 7/27/2009 4 comments Cswitch Corp. made waves and headlines in 2006 when it unveiled a novel configurable array architecture said to be capable of narrowing the performance and density gaps between field-programmable gate arrays and application-specific ICs.
Xilinx Virtex-6 FPGA User Guide Lite Design How-To 7/22/2009 2 comments This paper gives potential users an easy-to-grasp idea of the device functions of Xilinx Virtex-6 FPGAs. It describes the functionality of these devices in far more detail than in the data sheet--but avoids the minute implementation details covered in the various Virtex-6 FPGA user guides.
Sigrity enhances IC package modeling pak Product News 7/22/2009 Post a comment Sigrity unveiled a new version of its XtractIM product that allows package designers to assess performance of signal and power delivery nets intuitively, characterize a broader set of package types, and extract electrical models with improved accuracy.
The business of IP: it ain't a bake sale Blog 7/22/2009 3 comments IP vendors have long maintained that theirs is a product business model. In the face of rising complexity and shrinking geometries, however, selling IP may no longer be about baking up a plate of brownies, sealing it in shrink wrap, and putting it out there for sale.
DAC showing for 'push-button' analog test Product News 7/21/2009 Post a comment Analog built-in-self-test specialist ATEEDA will be seeking to woo fabless companies at DAC 2009 with an EDA tool that automatically generates HDL or Verilog code to add analog BIST capabilities to mixed signal silicon.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments