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posted in July 2012
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Altera shipping 14.1 Gbps backplane-capable transceivers in 28-nm Stratix V FPGAs
Product News  
7/31/2012   Post a comment
The only FPGA with 14.1 Gbps backplane-capable transceivers to meet the high-performance requirements in test and measurement, data centers, and storage area networks.
Statistics, statistics and damned lies
7/31/2012   15 comments
Piracy is a series issue, but I get annoyed when people twist statistics in ways that support their opinion and don’t stick to the facts…
Have you got the globes? No, I always walk this way!
Programmable Logic DesignLine Blog  
7/31/2012   31 comments
You tend to forget just how much more information there seems to be when you are looking at globe as opposed to a flat map / projection.
Synopsys buys EDA vendor Ciranova
News & Analysis  
7/30/2012   Post a comment
EDA and IP vendor Synopsys announced the acquisition of custom IC EDA tool vendor Ciranova. Terms of the acquisition were not disclosed.
The 2012 Olympics opening ceremony … WOW!
Programmable Logic DesignLine Blog  
7/30/2012   27 comments
Did you see the opening ceremony for the 2012 Olympic Games on Friday? I have to say that I was completely blown away…
Lattice announced serial image sensor bridge support for Sony IMX136/104
Product News  
7/30/2012   3 comments
Design uses low cost, low power MachXO2 PLD
Best of the web -– July 27th
7/27/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
What were they thinking: Brain Optimization
7/27/2012   3 comments
We see Groupons for everything these days, but this one really caught my eye. Can someone really perform brain optimization on me…
First public access release to Xilinx Vivado design suite
Product News  
7/26/2012   2 comments
Accelerates time to implementation from C and RTL up to 4x and improves performance up to 15 percent.
What’s happening at OCP-IP
7/26/2012   2 comments
Ian Mackintosh updates me about four developments in the world of OCP-IP and a sneak peak at his new book on management…
Cadence CEO sees design activity keeping pace
News & Analysis  
7/26/2012   Post a comment
Cadence Design Systems President and CEO Lip-Bu Tan said he expects to see design activity remain at a good pace in the second half of the year, despite macroeconomic challenges.
No! It's not fair!
Programmable Logic DesignLine Blog  
7/25/2012   10 comments
I really don’t think it's "cricket" for people to tempt me in this way, because I am a weak man…
Low-power webinars worth watching
7/25/2012   3 comments
Please disregard the man behind the curtain, this low power webinar series is worth listening to, but if you read the description it may scare you away…
EDA/IP Weekly Roundup – July 25th
7/25/2012   Post a comment
Mentor, Aldec, TVS, TSMC, ARM, S2C, Esterel, Synopsys and TowerJazz made the lineup today. See here for their news…
Opinion: Relationships matter
7/24/2012   2 comments
What is the value of hiring a public relations specialist? Priceless according to Nanette Collins who points out several ways in which they can help…
Is an emphasis on games a sign of decadence?
7/24/2012   17 comments
Are games for children and something to be put aside when we get older and life gets serious? Or should life never get serious? And how does electronics play into that?
Power awareness in RTL design analysis
Design How-To  
7/23/2012   1 comment
power intent awareness plays a critical role in verification and analysis of different aspects of the RTL design…
MeeGo smartphone firm emerges from Nokia
News & Analysis  
7/23/2012   8 comments
Former employees from Nokia's MeeGo N9 organization have formed an independent smartphone product company called Jolla Oy. The company has announced a sales and distribution agreement with D.Phone Group, a chain of mobile phone shops in China.
Using code-coverage analysis to verify 2D graphic engines in automotive apps
Design How-To  
7/20/2012   1 comment
A design engineer describes metric-driven verification and the benefits of code-coverage analysis.
Free "Introduction to Electronics" online training course
7/20/2012   13 comments
Yours truly will be presenting five 1-hour sessions – one a day Monday through Friday – each starting at 2:00pm Eastern Time (which is 11:00am Pacific Time, or 7:00pm UCT/GMT).
Best of the web -– July 20th
7/20/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
What were they thinking: Cures for jet lag
7/20/2012   12 comments
As I prepare for my annual pilgrimage to England, I wondered about the advances in cures for jet lag...
Yum Yum – canned uranium ore!
Programmable Logic DesignLine Blog  
7/18/2012   18 comments
The really funny thing about this can of uranium ore webpage is the associated comments, for example...
EDA/IP Weekly Roundup – July 18th
7/18/2012   Post a comment
EVE, Synopsys, Breker, Xylon, Lattice, Microsemi, Xilinx and Cadence made the lineup today. See here for their news…
Atrenta talks about power
7/17/2012   Post a comment
There are three main power activities that we are involved with – estimation, optimization and verification. We are also working on power intent reconciliation…
Mommy, why does that man smell like coconuts?
Programmable Logic DesignLine Blog  
7/17/2012   8 comments
In which we explore a "do-it-yourself" recipe for underarm deodorant that features coconut oil as a binding agent…
Xilinx Artix-7 FPGAs – For applications on the "edge"
Product News  
7/17/2012   Post a comment
Xilinx Artix-7 sets a new FPGA performance standard for power and cost, raising the performance bar for portable and small form factor applications at the ‘Edge’.
Atomic Rules – OK?
News & Analysis  
7/17/2012   4 comments
Atomic Rules Expands Technical Staff with Internship Hire of University of Arkansas grad student Christina Smith.
Accellera make new version of SystemC library available
7/17/2012   Post a comment
Accellera adds new capabilities to its SystemC proof-of-concept library including support for transaction-level modeling…
Assembler optimized software libraries for TI DSPs
Product News  
7/16/2012   Post a comment
Assembler optimized products includes a DSP Vector Library; an ECC LINPACK Library, an EISPACK Library and an ECC BLAS Level 1/2/3 Library.
Energy Micro opens design center in Kraków, Poland
News & Analysis  
7/16/2012   Post a comment
Engineering team already in place to develop embedded software and radio protocols.
Want to learn FPGAs? Special $34.94 dev board offer!
7/16/2012   4 comments
Wow! A Papilio One 250K FPGA Development Platform for only $34.94 (plus very affordable shipping and handling).
Is the cost reduction associated with IC scaling over?
7/16/2012   9 comments
The cost reduction associated with scaling may be over, unless we augment dimensional scaling with monolithic 3D-IC scaling.
Do NOT push the big red button!
7/16/2012   10 comments
You just know that someone is going to push the big red button to see what happens… it's only a matter of when…
EDA firm gets funding after nine years
News & Analysis  
7/16/2012   3 comments
Breker Verification Systems of Mountain View, California, an EDA company that provides verification software for system-chips, has announced it has raised $5 million in Series A funding from Astor Capital Group.
Control dominated design
Design How-To  
7/14/2012   2 comments
So you think high-level synthesis is just for dataflow? Think again after Forte shows you how it can help you with control-dominated design…
Best of the web -– July 13th
7/13/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
What were they thinking: Tech-talk
7/13/2012   5 comments
The English love to make fun of things, including technology and themselves. This BBC video does both perfectly...
High praise for Alfa Insurance
Programmable Logic DesignLine Blog  
7/12/2012   14 comments
I just returned from a quick trip down to my local Alfa Insurance office, and I have to say that I am mega-impressed…
A "must read" new book – The Violinist’s Thumb by Sam Kean
Programmable Logic DesignLine Blog  
7/12/2012   Post a comment
There are genes to explain crazy cat ladies, why other people have no fingerprints, and why some people survive nuclear bombs...
Camera kit for automotive black box recorders from Lattice and friends
Product News  
7/12/2012   2 comments
New black box camera kit from Lattice Semiconductor and Leopard Imaging enables video processor from Texas Instruments to interface to two 720p image sensors.
XpressGX5LP low profile PCIe FPGA design kit from PLDA
Product News  
7/11/2012   Post a comment
Based on Altera Stratix V GX FPGA, new half-height board delivers PCIe 3.0 x8, 40G Ethernet and DDR3 SDRAM interfaces, enabling quick time-to-market
Altera introduces new 40GbE/100GbE IP core
Product News  
7/11/2012   Post a comment
New 40GbE/100GbE IP core provides a complete solution for customers integrating Ethernet into their FPGA-based systems.
Xilinx to invest $50M expanding operations in Ireland
News & Analysis  
7/11/2012   Post a comment
Xilinx will recruit 60 highly qualified new staff for Dublin and Cork
Increase your FPGA design skills for free
Product News  
7/11/2012   2 comments
I recently received a jolly friendly email from the folks at Altera inviting us to partake of their free online technical training courses…
I want a Jumbo Jet Executive Desk!
Programmable Logic DesignLine Blog  
7/11/2012   5 comments
I've said it before and I'll say it again – I LOVE the stuff they do over at MotoArt...
EDA/IP Weekly Roundup – July 11th
7/11/2012   Post a comment
Mentor, Synopsys, SMIC, Altera, Aldec, Agilent and Cadence made the lineup today. See here for their news…
EDAC reports 6.3% growth for Q1 2012
7/11/2012   1 comment
Services drags down the numbers but EDAC still shows good growth in most categories…
Hot news! Lattice announces strategic partnership with UMC
News & Analysis  
7/10/2012   Post a comment
New strategic partnership leverages the non-volatile memory technology Lattice recently acquired as a result of its acquisition of SiliconBlue.
Enabling error resilience throughout the embedded system
Design How-To  
7/10/2012   Post a comment
FPGAs connected to gigabytes of DDR is now common, so attention must be paid to the probability and avoidance of soft errors.
Page 1 / 2   >   >>

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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