SoC-based designs challenge traditional design flows Design How-To 8/30/2002 Post a comment When the semiconductor division of Philips undertook the ambitious task of designing a family of microcontrollers that would remove all the impediments to migration from 8- to 32-bit architectures, we knew that our primary objective was to eliminate the cost barriers while at the same time ensuring deterministic, real-time performance and adequate bandwidth in a package small enough to be deployed in a variety of small-footprint embedded control applications.
Method ensures on-track designs News & Analysis 8/19/2002 Post a comment Achieving functional closure on register-transfer-level designs continues to be one of the greatest challenges for today's ASIC and system-on-chip design teams.
ASIC design flow gives CPU core custom performance Design How-To 8/19/2002 Post a comment The ever-increasing levels of CPU performance demanded by embedded applications and product design cycles that have often been reduced to only a few months, have made it important to produce synthesizable processor cores capable of execution speeds typically only achievable by complex custom solutions.
CAUTION: Mandatory Methodology Shift Ahead Design How-To 8/8/2002 Post a comment The spiraling expense and design time associated with chips fabricated
in ever-shrinking design technologies is impacting how and when a chip
designer hands off a design to the system designer. Tera Systems' Mark
Miller discusses the pros and cons of RTL and gate-level handoff and how both require early awareness of the implications of the design's micro architecture along with high-quality RTL code.