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Content tagged with Design Tools (EDA)
posted in August 2003
Straightforward DDR SDRAM Connection to FPGAs Using IP
News & Analysis  
8/28/2003   Post a comment
Double Data Rate (DDR) SDRAM is now the most popular memory type for designers of embedded applications needing large amounts of low-cost, high-performance memory. Thanks to widespread adoption by the PC industry, and improved long-term availability over SDR SDRAM, it also makes good commercial sense for use in today's applications.
Configurable processors or RTL -- evaluating the tradeoffs
Design How-To  
8/27/2003   Post a comment
Should you design acceleration blocks with RTL, or choose a configurable processor? Tensilica engineer Del Miranda reports examples that show the advantages, and tradeoffs, of both approaches.
Structured-ASIC debate building in fervor
News & Analysis  
8/25/2003   Post a comment
A custom-chip design approach that was initially dismissed by critics as a fad is proving to have staying power as system architects increasingly seek a middle ground between cell-based designs and FPGAs. Crista Souza has these insights.
Non-Classical CMOS: the "Ultimate" MOSFET Device
Design How-To  
8/22/2003   Post a comment
The key electronic component in the integrated circuit (IC) is the planar, bulk metal-oxide semiconductor field-effect transistor (MOSFET).
SOI and strained silicon complement each other
News & Analysis  
8/22/2003   Post a comment
For the past 25 years, geometric scaling of silicon CMOS transistors has enabled not only an exponential increase in circuit integration density — Moore's Law — but also a corresponding enhancement in the transistor performance itself.
High-k strides reopen door to germanium
News & Analysis  
8/22/2003   Post a comment
In the beginning there were bipolar transistors made on germanium wafers, though semiconductor makers quickly switched to silicon as the prime semiconducting material.
Silicon germanium challenges metrology
Design How-To  
8/22/2003   Post a comment
To enable continued migration to smaller design rules in advanced CMOS processes, the semiconductor industry must deal with a proliferation of materials-from 20 materials options at the 130-nanometer node to nearly double that at the 65-nm node.
Right on time -- requirements for advanced custom design
News & Analysis  
8/22/2003   Post a comment
Custom IC design is becoming phenomenally more complex. In this whitepaper, Cadence Design Systems authors Lavi Lev and Ted Vucurevich analyze today's custom design flow and propose a new "advanced custom design" methodology that combines accuracy with fast turn-around times.
Inside composite substrates
News & Analysis  
8/22/2003   Post a comment
In contrast to the current generation of bulk wafers, which typically are pure silicon, "engineered" substrates contain several materials layered one on top of the other.
Engineered substrates boost performance
Design How-To  
8/22/2003   Post a comment
he race of the best-in-class chip makers toward the 65-nanometer and 45-nm technology nodes has accelerated the need for the integration of new materials such as metal oxides, porous low-k oxides, new silicides, metal gates and the like.
Crafting wafer-scale strained silicon
Design How-To  
8/22/2003   Post a comment
Strain affects the band structure of semiconductor materials, allowing the alteration of properties dictated by nature.
Programmable analog chases discrete market pricing
News & Analysis  
8/19/2003   Post a comment
This isn't exactly "I told you so." Or maybe it is: Anadigm is dropping the entry price for its programmable analog chips below $5 to be more competitive with the discrete devices that they are designed to replace. Crista Souza reports.
Free PCB CAD tool gets upgrade
News & Analysis  
8/19/2003   Post a comment
Analog/mixed-signal optimization tool supports 1394 PHY design
News & Analysis  
8/18/2003   Post a comment
The analog IC designer must constantly juggle tradeoffs between power, noise, silicon area, and bandwidth, says Analog Design Automation. The ability to evaluate a number of separate designs in the same EDA flow " and to display the results graphically on the same screen " helps the designer balance tradeoffs and improve time to market. This article, from the August 18th issue of PA magazine, suggests how.
Tips for firmware-friendly register design
Design How-To  
8/14/2003   Post a comment
Adding further detail to his previous tutorials, LSI Logic's "firmware friendly" engineer, David Fechser, shows you how to design register bit fields and handle "Go" bits in a way that facilitates firmware design.
Accellera's ALF language lets designers control libraries
News & Analysis  
8/8/2003   Post a comment
Tired of just taking library elements "as is?" NEC's Wolfgang Roethig shows how Accellera's Advanced Library Format (ALF) modeling language gives chip designers more access to, and control over, ASIC and SoC libraries.
It's Time to Return to 10x Passion
Blog  
8/6/2003   Post a comment
As the leaders of the high-tech industry emerge from their bubble bust and lingering budget hangovers, they will once again start yearning for the good old days when their EDA suppliers were focused and were investing in the next 10x gain in productivity and predictability. The truth is that achieving the next 10x will take innovation and conviction.
Why We Don't Have IP Quality Yet
Blog  
8/6/2003   Post a comment
IP quality has now become an overall issue in the IC industry, because the predictions that organizations like VSIA made back in the mid 1990s have become reality. The combination of the convergence of electronic products, coupled with the relentless march to chips that can contain tens of millions of gates today, is making the integration of internal and 3rd party IP the only economically viable way to create the next generation chips.
PCB East announces 2003 program
News & Analysis  
8/5/2003   Post a comment
Startup unwraps power grid planning software
News & Analysis  
8/4/2003   Post a comment
Turning adversity into opportunity, a design engineer laid off last year has used his lighter schedule to develop a block-level power grid noise simulator he had thought about for years. Donald Bennett formed RLCSim Co. (Lochore, Scotland) to market the tool, named RLCSim, which Bennett described as the market's first pre-layout planning tool.
Analyzing inductive noise in power grids
Design How-To  
8/1/2003   Post a comment
Inductance in IC interconnects is a serious problem for GHz designs. This article by Donald Bennett, principal of EDA startup RLCSim Company, shows how transmission line theory techniques can be used at the pre-layout stage to analyze resistive, inductive and capacitive effects.


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1 Comment
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