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Content tagged with Design Tools (EDA)
posted in August 2004
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Xpedion to use new funds for RFIC tool development
News & Analysis  
8/31/2004   Post a comment
Xpedion President and CEO Pete Rodriguez said the company will use the new venture funds in preparation for the launch of its second-generation GoldenGate RFIC analysis tool.
Xpedion gets funding from veteran EDA investors
News & Analysis  
8/30/2004   Post a comment
Privately-held RF IC simulator vendor Xpedion Design Systems Inc. announced it has secured a new round of venture funding.
Why you should outsource IC rule decks
News & Analysis  
8/30/2004   Post a comment
Outsourcing IC physical verification rule deck qualification to expert consultants can provide objectivity, competency and accuracy, says Mentor Graphics' Bill Martin.
Correlating behavioral cycle time with HDL simulation
News & Analysis  
8/28/2004   Post a comment
Transaction-based behavioral models speed verification, but correlating behavioral cycle time with HDL simulation time is tough. In this tutorial Debra Klopfenstein (right), a verification engineer at Silicon Graphics, uses a simulation example to show you how to do that.
EDA-Markterholung noch nicht in trockenen Tüchern
News & Analysis  
8/27/2004   Post a comment
Für das erste Quartal meldete die EDA-Branche ein Wachstum von 6 Prozent. Doch noch ist es zu früh, um die Sektkorken knallen zu lassen. Denn der Großteil des Wachstums ging nicht auf EDA-Produktverkäufe zurück und fand auch nicht in Nordamerika, Europa oder Japan statt.
Mentor kauft Speicher-IP von Palmchip
News & Analysis  
8/27/2004   Post a comment
Mentor Graphics hat Palmchips Geschäftszweig für geistiges Eigentum (IP) für parallele und serielle ATA-Speicherlösungen übernommen. Wie tief Mentor dafür in die Tasche greifen musste, blieb geheim.
Synopsys faces shareholder suits
News & Analysis  
8/26/2004   Post a comment
Several law firms have filed or have indicated their intent to file shareholder class-action lawsuits in the wake Synopsys' drastic stock price drop last week.
Stratos Lightwave performs testing and eval services for opto systems
Product News  
8/25/2004   Post a comment
Stratos Lightwave LLC has announced new services for performance testing and verification of opto-electronic products and systems used in harsh operating environments, specifically for military, commercial aviation, or industrial applications. These product testing and evaluation services provide optical system designers with validation of proper optical performance, environmental testing, and failure analysis.
Actel, Mentor improve FPGA synthesis
News & Analysis  
8/24/2004   Post a comment
FPGA vendor Actel and Mentor Graphics have announced the latest version of Mentor's Precision RTL synthesis tool.
Video/image processing Blockset brings model-based design to embedded apps
Product News  
8/23/2004   Post a comment
Targeting embedded video and image processing systems, The MathWorks' Video and Image Processing Blockset allows imaging engineers to rapidly build models, simulate algorithms and system behavior, generate C-code for deployment on programmable processors, and verify their designs, all within the Simulink environment.
Mentor Graphics plans new Indian subsidiary
News & Analysis  
8/23/2004   Post a comment
Mentor Graphics Corp. will form a new Indian company to handle direct sales and support activities.
Carbon teams with Simics for speedy system validation
News & Analysis  
8/20/2004   Post a comment
Carbon Design Systems Inc., a speedy hardware model generation tool startup, said it has integrated its DesignPlayer cycle and register accurate engine with Virtutech Inc.'s Simics Instruction Set Simulator.
Synplicity names Meyers new president
News & Analysis  
8/20/2004   Post a comment
Synplicity Inc. has named Gary Meyers, the head of its worldwide sales organization, president and chief operating officer.
Synopsys korrigiert Umsatz und Ertrag nach unten
News & Analysis  
8/20/2004   Post a comment
Ist die Erholung der EDA-Branche bereits wieder am abklingen? Die jüngsten Finanzreports von Synopsys sprechen dafür.
PCB guru Ritchey offers high-speed design course
News & Analysis  
8/20/2004   Post a comment
Noted design guru Lee Ritchey will conduct a two-day course in high-speed PCB and system design disciplines October 18-19 in Marlborough, Mass.
Hard macros will revolutionize SoC design
News & Analysis  
8/20/2004   Post a comment
A surprising proliferation of hard macros has become a "quiet revolution" in SoC design, say Monterey Design Systems authors including CTO Enno Wein (right). This article shows why it's happening, and how it will impact chip cost and design.
Riding the 'wave' of 90nm signal integrity
News & Analysis  
8/20/2004   Post a comment
Designers must analyze signal-integrity problems at the IC, package, and PCB levels concurrently, and move to model-based, full-wave extraction, says Optimal's Ching-Chao Huang.
La reprise de la CAO s’essouffle : Synopsys revoit ses estimations à la baisse pour 2005
News & Analysis  
8/20/2004   Post a comment
Dans le contexte d’une reprise de l’industrie de la CAO qui semble arriver à bout de souffle, Synopsys Inc. annonce un manque à gagner pour le troisième trimestre et réduit de 80 millions de dollars et de 450 millions de dollars ses estimations de chiffre d’affaires pour 2004 et 2005.
eInfochips to open new design center in India
News & Analysis  
8/19/2004   Post a comment
eInfochips, a provider of ASIC design services, embedded systems solutions and IP cores and is opening a new design center in Pune near Mumbai.
Synopsys cuts revenue estimates
News & Analysis  
8/19/2004   Post a comment
In a sign the EDA industry recovery may be losing steam, Synopsys Inc. announced a third-quarter revenue shortfall and cut $80 million from its fiscal 2004 and $450 million from its 2005 revenue estimates.
ZiLOG Adds ROM-based items to Crimzon MCU line
Product News  
8/18/2004   Post a comment
ZiLOG, Inc. has rolled-out its Crimzon MCU Family of infrared microcontrollers. Available immediately, the ZLR16300 devices are 100 percent software compatible with ZiLOG's current Crimzon family of OTP-based IR MCUs.
Embedded 64-Bit MPUs -- The Myths and Realities
Product News  
8/17/2004   Post a comment
Opinion: Jerry Worchel principal analyst, Digital Engines Service, In-Stat/MDR sees a bright future for 64-bit microprocessors down the road. As the capabilities and demands on the Internet and wireless communications begin to rapidly expand into a broader breadth of functional offerings, the requirement for wider processor bus widths will rapidly follow, according to Worchel.
ARM acquiert la société Axys Design Automation
News & Analysis  
8/16/2004   Post a comment
ARM Holdings PLC, spécialiste des microprocesseurs RISC 16/32 bits intégrés dans les systèmes de communication, a annoncé lundi (16 août) l’acquisition d’Axys Design Automation Inc., fournisseur de processeurs et d’outils de simulations. Aucun détail financier n’a été révélé.
Tharas offers monthly rental for sim acceleration
News & Analysis  
8/16/2004   Post a comment
Hardware-assisted verification vendor Tharas Systems Inc. is offering customers flexible subscription licensing for its Hammer 100 simulation acceleration system.
'Divide and conquer' with verification IP
News & Analysis  
8/13/2004   Post a comment
Verification IP for standard chip interfaces can provide a tremendous productivity boost, says Denali's Kevin Silver. Here's what's needed to make it successful.
Improving yields without compromising area
News & Analysis  
8/13/2004   Post a comment
Design for manufacturability (DFM) often brings design rules that conflict with area minimization goals, says Prolific CEO Paul de Dood (right). In this article, he shows how design rules can balance yield and area concerns.
Design-Optimierung: AFP Technology erzielt kleinere Chip-Flächen
News & Analysis  
8/13/2004   Post a comment
Um der für Massenmärkte typischen Forderung nach günstigen Preisen gerecht zu werden, hat Toshiba die AFP Technology zur Verkleinerung seines 8 Millionen Gatter enthaltenden Mpeg2-Codec MeP-LSI-Chips eingesetzt. Damit gelang eine Verkleinerung um 10,5 Prozent.
Cadence links PSpice to Matlab
News & Analysis  
8/11/2004   Post a comment
Linking two widely-used electronic design products, Cadence Design Systems has announced an interface between its PSpice analog simulator and the Matlab modeling tool from The Mathworks. The interface allows the co-simulation of electrical and mechanical systems.
Ratford leaves Giga Scale to head AccelChip
News & Analysis  
8/11/2004   Post a comment
EDA veteran Vin Ratford has left tiny floorplanning startup Giga Scale Integration Corp. to become the new president and CEO of AccelChip.
Spice algorithm analyzes high-gain feedback
News & Analysis  
8/9/2004   Post a comment
Extending Spice to realms where ac analysis has been difficult, Intusoft CEO Larry Meares has developed an algorithm that promises dc convergence for circuits with cascaded high-gain amplifiers. The algorithm is being incorporated into Intusoft's IsSpice4 simulator.
EEsof rolls advanced EDA test
Product News  
8/9/2004   Post a comment
Agilent Technologies is debuting new EDA capabilities that enable simulation and verification of wireless LAN, 3GPP, and TD-SCDMA circuit designs. Agilent is introducing wireless test benches, sources, and measurement capabilities for its existing Advanced Design System 2004A EDA software from EESof.
Getting inside the SiP
News & Analysis  
8/9/2004   Post a comment
Many design teams are taking a harder look at the system-in-package alternative to conventional system-on-chip design. The advantages of combining multiple dice in one package have been well-documented.
Cu links on the straight and narrow
News & Analysis  
8/9/2004   Post a comment
Semiconductor devices now operate at internal clock speeds that far outstrip the electronic interconnection infrastructure's ability to support them. Although optoelectronic technologies have been considered as potential solutions for short-range transmission, serious impediments remain, with high cost and power near the top of the list. Traditional copper technology appears to be a better choice for now.
SiPs pose considerations for die design
News & Analysis  
8/9/2004   Post a comment
Semiconductor technology has always been driven by the need for enhanced features and functionality, while reducing size and cost. While system-on-chip technology promises many advantages to system architects and designers, system-in-package has become the more practical approach to miniaturization in many cases today.
A systems approach delivers SiP design
News & Analysis  
8/9/2004   Post a comment
The soaring popularity of cellular telephones and digital still cameras, with their demand for small-form-factor semiconductor packages, has made system-in-package (SiP) solutions increasingly popular. But SiP isn't just about size: Because each functional chip can be developed individually, SiP means faster development and lower cost than a system-on-chip (SoC), which must be developed as one large single-chip design.
Analog BIST locates good dice
News & Analysis  
8/9/2004   Post a comment
System-in-a-package technology is, by definition, driving the need for multiple dice in the same package. This trend, in turn, is driving the need for known-good dice.
Management of Technical Details Further Enhances Benefits of System-In-Package (SIP) Technology
News & Analysis  
8/9/2004   Post a comment
There are many trade-offs to consider when making an integration decision between system-in-package and system-on-chip technologies. Generally, SoC offers the primary benefits of reduced costs and improved system performance through the design and optimization of multiple disparate system functions on a single die. SoC devices are generally driven by a requirement for increased system performance, reduced cost and/or smaller size.
Component Partitioning for System in Package (SiP) Applications
News & Analysis  
8/9/2004   Post a comment
Timely and effective development of system-in-package (SiP) alternatives has driven the need for broader supplier collaboration on system-partitioning decisions within the electronics food chain. Unlike earlier generations of electronics with individually packaged components, packaging subcontractors and semiconductor device manufacturers today must work together to define the most effective partition options available.
SiP vs. SoC
News & Analysis  
8/9/2004   Post a comment
SiP vs. SoC
My Spice lied to me! Why is this such a common complaint?
Design How-To  
8/7/2004   Post a comment
Take a precision razor (the Spice engine), insert a crappy blade (the Model); the result will be a guaranteed terrible shave, says this analog rascal. Those of you who remember Bill Pacoe's colorful and informative talks at the Analog and Mixed-Signal Applications Conferences will find this an interesting reprise.
Is SystemVerilog the next PL/1?
News & Analysis  
8/6/2004   Post a comment
Design and verification are two distinct tasks that should not be forced into a single language, says Tommy Kelly, CEO of consulting firm Verilab, in this contrarian view of SystemVerilog.
Modeling and design techniques reduce 90 nm power
News & Analysis  
8/6/2004   Post a comment
With small feature sizes, designers must work harder to reduce dynamic and leakage power. Magma Design Automation's Robert Jones (right) presents design and modeling techniques, mostly using multiple or variable voltages, that will help reduce power challenges.
IC design conference calls for papers
News & Analysis  
8/6/2004   Post a comment
The International Symposium on Physical Design (ISPD) has issued a call for papers, and has announced that next year's conference will be held April 3 " 6 at the Marine Memorial Hotel in San Francisco, Calif. A premier showcase for research in IC physical design, ISPD draws attendees from industry and academia.
Synthesis suite targets unconventional designs
News & Analysis  
8/6/2004   Post a comment
FTL Systems is quietly preparing a complete IC design solution, but this small, privately held company isn't about to go head-to-head against the big EDA vendors. Instead, the company said it is focusing on problems that conventional EDA tools can't solve — most notably ICs that are asynchronous or require radiation hardening or have huge gate counts.
SafeNet rolls mobile security suite for TI OMAP processor
Product News  
8/6/2004   Post a comment
SafeNet has released a software development kit Wednesday (August 4) that allows designers to secure mobile phones developed around Texas Instruments OMAP5912 baseband processor.
Fujitsu und Cadence feilen gemeinsam an SoCs
News & Analysis  
8/5/2004   Post a comment
151 Der japanische Halbleiterhersteller Fujitsu und der EDA-Anbieter Cadence Design Systems wollen gemeinsam eine neue SoC-Designumgebung entwickeln. Die beiden Unternehmen haben zu diesem Zweck eine weltweite Partnerschaft abgeschlossen.
Mohsen pleads not guilty as judges abandon case
News & Analysis  
8/4/2004   Post a comment
Facing 23 criminal counts including solicitation to murder a federal judge, former Aptix CEO Amr Mohsen entered not guilty pleas on all counts at an arraignment Wednesday (Aug. 4). But there was no judge to hear them, because all judges in the Northern District of California have recused themselves from the case.
Prolific to team with DongbuAnam on tools, IP
Product News  
8/4/2004   Post a comment
Prolific Inc., a provider of automated standard cell creation software, has announced a partnership with pure-play wafer foundry DongbuAnam Semiconductor covering software, standard cell IP, and implementation services for the latter company's advanced digital and mixed-signal technologies.
Une jeune pousse française de CAO cible la conception sur mesure
News & Analysis  
8/4/2004   Post a comment
De la recherche doctorale à l’Université de Paris, au logiciel commercial de CAO vendu à l’échelle mondiale, il y a un pas à franchir. La jeune pousse française de CAO Avertec franchit ce pas en inaugurant un nouveau bureau aux États-Unis et en proposant sa technologie d’intégrité du signal.
Synopsys prévoit un manque à gagner pour le troisième trimestre
News & Analysis  
8/4/2004   Post a comment
Selon un avertissement émis le lundi 2 août, Synopsys n’atteindra pas les prévisions de bénéfice net et de recettes pour le troisième trimestre de l’exercice clos le 31 juillet 2004. Synopsys, qui avait dépassé l’an dernier son principal rival, Cadence Design Systems, en termes de recettes totales, pourrait maintenant perdre son avance.
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