Breaking News
Content tagged with Design Tools (EDA)
posted in August 2006
Page 1 / 2   >   >>
Jasper offers free verification planning tool
News & Analysis  
8/30/2006   Post a comment
Verification-focused EDA startup Jasper Design Automation is making available a free tool for tracking the progress of verification plans.
Reference design provides functionality for flat-panel digital TV
Product News  
8/30/2006   Post a comment
LSI Logic and Micronas offer reference design that provides all of the functionality required for a high-quality, feature-rich, flat-panel integrated digital TV.
Smaller is better
Blog  
8/30/2006   Post a comment
A consortium has introduced a design kit for low-power 45 nm process technology. Do we need it so soon?
Zilog offering free development suite
Product News  
8/29/2006   Post a comment
Microprocessor and 8-bit microcontroller supplier Zilog announced that it has made available its Zilog Developer Studio II, free of charge, on the company's Web site.
DVCon calls for paper, panel, tutorial proposals
News & Analysis  
8/29/2006   Post a comment
Organizers of the 2007 Design and Verification Conference have issued a call for paper, panel and tutorial submissions.
Agilent completes Xpedion acquisition
News & Analysis  
8/28/2006   Post a comment
Agilent Technologies has completed the acquisition of privately held EDA vendor Xpedion Design Systems. Financial details were not disclosed.
Don't look at India as low-cost talent
Blog  
8/28/2006   Post a comment
The electronics industry should not look at the talent pool in India as a low-cost solution, writes an Indian-born engineer.
Aprio contributes DFM technology to Si2
News & Analysis  
8/28/2006   Post a comment
Design-for-manufacturability-focused startup Aprio Technologies has signed an agreement with the Silicon Integration Initiative to contribute lithography process modeling and simulation technology to Si2's Design to Manufacturing Coalition.
Xilinx tool claims to extend Virtex-5 performance
Product News  
8/28/2006   Post a comment
Programmable logic giant Xilinx announced the availability of the 8.2 version of its PlanAhead hierarchical design and analysis software with support for its newest Virtex-5 LX family of 65-nanometer FPGAs.
Solving the toughest problems in CDC analysis
Design How-To  
8/28/2006   Post a comment
FIFO and handshake synchronizers pose special difficulties; new tools using static and functional analysis are the answer
Si2 seeks static format extension proposals
News & Analysis  
8/25/2006   Post a comment
The Silicon Integration Initiative has issued a request for technology, seeking proposals for providing extensions to current formats and languages to support statistical timing.
Startup Oasis to name EDA vet VP of sales
News & Analysis  
8/25/2006   Post a comment
Oasis Tooling, a two-year old startup created to commercialize technology for companies adopting Oasis as a replacement for the GDSII file format, plans to appoint 25-year EDA veteran Roger Bitter vice president of worldwide sales next week.
Ansoft profit up 96% year-to-year
News & Analysis  
8/24/2006   Post a comment
EDA vendor Ansoft posted a fiscal first quarter net income of $2.3 million on a generally accepted accounting principles basis for its first quarter of fiscal 2007, up 96 percent year-to-year.
EDA poised to grow faster than IC market, analyst says
News & Analysis  
8/24/2006   Post a comment
The increase in IC design cost the 65-nanometer node presents an opportunity for EDA, which can increase its growth rate if it can provide more productive solutions, according to Handel Jones, CEO of International Business Strategies.
International Conference on Computer Aided Design (ICCAD) previews technical program
News & Analysis  
8/24/2006   Post a comment
The ICCAD conference, to be held November 5 - 9 in San Jose, will focus on today's challenges and emerging technologies
Scanner slashes automotive body data capture time
Design How-To  
8/23/2006   Post a comment
Computers often limit designers, so clay models give them the freedom they need. Laser scanning has helped a major performance automobile manufacturer reduce time to capture complex surface geometries from such models by 75%.
A tutorial on incremental design using FPGAs from Actel
Design How-To  
8/23/2006   Post a comment
An "incremental" design flow is highly desirable with regard to repairing or optimizing parts of the design without disturbing portions that have met their design requirements.
Patents in Magma-Synopsys dispute may be reexamined
News & Analysis  
8/23/2006   Post a comment
Magma Design Automation said that the U.S. Patent and Trademark Office has been asked to re-examine U.S. Patents No. 6,453,446 and 6,725,438 (the '446 and '438 patents)--two of the three patents at the core of the ongoing bitter patent dispute between Magma and Synopsys Inc.
Patents in Magma-Synopsys dispute may be reexamined
News & Analysis  
8/23/2006   Post a comment
Magma Design Automation said that the U.S. Patent and Trademark Office has been asked to re-examine U.S. Patents No. 6,453,446 and 6,725,438 (the '446 and '438 patents)--two of the three patents at the core of the ongoing bitter patent dispute between Magma and Synopsys Inc.
How RF SiP technology is moving into the wireless design mainstream
Design How-To  
8/22/2006   Post a comment
To facilitate a move to mainstream SiP implementation, an integrated, scalable SiP design solution must be developed and reference flows provided.
Microchip offers debugging capabilities for PIC MCUs
Product News  
8/22/2006   Post a comment
Microchip Technology Inc.'s PICkit 2 development programmer now supports in-circuit debugging of selected Microchip PIC microcontroller products. This enables engineers, students and anyone with an interest to easily begin development and evaluation with PIC microcontrollers for a very low initial investment.
FPGA tool expands parallel programming capability
Product News  
8/21/2006   Post a comment
Programmable logic supplier Actel rolled out its third-generation FPGA programming tool, Silicon Sculptor 3.
Virtual prototyping speeds mixed-signal IC design
Design How-To  
8/21/2006   Post a comment
Virtual prototyping has been adopted for large digital designs, but has not yet extended to analog/mixed-signal designs, notes Cadence Design Systems' Raja Mitra. He shows how analog virtual prototyping could work.
Analysts unmoved by strong Synopsys quarter
News & Analysis  
8/18/2006   Post a comment
Synopsys' stock closed downward for two consecutive days following a strong fiscal third quarter earnings release. Investment analysts remain unenthusiastic but the company's prospects for significant short-term growth.
EDA startup names VP of sales
News & Analysis  
8/18/2006   Post a comment
EDA and intellectual property startup Silistix has named Thomas Katherman vice president of worldwide sales.
The sub-100-nm imperative: parametric yield ramp
Design How-To  
8/18/2006   Post a comment
When targeting sub- 100nm processes designers must consider yield factors before they release a design to manufacturing.
PTO rejects all claims of key patent in Synopsys-Magma fight
News & Analysis  
8/17/2006   Post a comment
The U.S. Patent and Trademark Office has rejected all 15 claims found in a Synopsys patent that is one of three patents at the heart of the high-profile dispute between Synopsys and Magma Design Automation.
EDA vets Hogan, Williams join startup's TAB
News & Analysis  
8/17/2006   Post a comment
Longtime semiconductor industry executive and venture capitalist Jim Hogan has joined the technical advisory board of EDA startup Dafca, as has Thomas Williams, a Synopsys Fellow and former IBM executive.
Hedge fund demands sale of Mosaid
News & Analysis  
8/17/2006   Post a comment
Loeb Partners, a New York-based hedge fund, has submitted a letter to fabless chip and intellectual property vendor Mosaid Technologies' board of directors, proposing that the company be sold.
Synopsys tops analyst expectations, bumps guidance
News & Analysis  
8/16/2006   Post a comment
Synopsys beat analyst expectations, posting a net income of $7.6 million on revenue of $277.2 million for its fiscal third quarter.
On-line evaluation tool simplifies implementing DDS semiconductors
Product News  
8/16/2006   Post a comment
On-line evaluation tool simplifies task of selecting, evaluating and implementing direct digital synthesis (DDS) semiconductors in applications ranging from test and measurement equipment to wireless and satellite communications.
Synopsys completes $20M acquisition of Sigma-C
News & Analysis  
8/16/2006   Post a comment
Synopsys Inchas completed the acquisition of German lithography simulation vendor Sigma-C Software in a cash transaction worth $20.5 million.
Cadence bars competitors from users' group meeting
News & Analysis  
8/15/2006   Post a comment
In a break from previous policy, Cadence Design Systems has not extended invitations to competing companies to participate in its users' group conference this year, EE Times has learned.
ESL startup joins Synopsys partner program
News & Analysis  
8/15/2006   Post a comment
Electronic system level-focused EDA startup Bluespec has joined the Synopsys in-Sync program to improve the design flow between Bluespec and Synopsys tools.
Silvaco, CSI settle long-running dispute
News & Analysis  
8/15/2006   Post a comment
Privately held EDA vendor Silvaco International has reached a settlement to end all litigation with Circuit Semantics, an EDA startup that went belly up two years ago, Silvaco said.
Mentor to deliver selected EDA technologies to Freescale
News & Analysis  
8/14/2006   Post a comment
Freescale aims to provide Manufacture-Aware Design methods at every phase of the chip design process, from architectural design to mask preparation.
DAC issues call for papers
News & Analysis  
8/14/2006   Post a comment
The organizers of the Design Automation Conference issued a call for papers for the 44th DAC.
Despite Cadence deal, Freescale turns to Mentor on DFM
News & Analysis  
8/14/2006   Post a comment
Despite naming Cadence Design Systems as its primary EDA vendor last year, Freescale Semiconductor has contracted with Mentor Graphics for design-for-manufacturability and design-for-test tools.
Verification challenges of embedded memory devices
Design How-To  
8/14/2006   Post a comment
Ramon Acosta, vice president of engineering at Nascentric, discusses the verification requirements of embedded memory and shows how next-generation fast Spice technology can help.
IRS wants another $324 million from Cadence
News & Analysis  
8/11/2006   Post a comment
An Internal Revenue Service review of Cadence Design Systems' federal tax returns for 2000 through 2002 concluded that the company owes an additional $324 million in taxes for the three-year period, according to a regulatory filing.
Mentor paid $5.3 million for Taiwanese EDA vendor
News & Analysis  
8/11/2006   Post a comment
EverCad, the Taiwanese circuit simulation/analysis tool provider that Mentor Graphics quietly acquired in January, carried a price tag of $5.3 million, according to a regulatory filing.
PCB design survey finds conflict between thermal, SI/EMC
News & Analysis  
8/11/2006   Post a comment
Electromagnetic compatibility and signal integrity design requirements for printed circuit board design are frequently conflict, according to the majority of respondents to a new survey of designers conducted by virtual prototype provider Flomerics.
Comment: Software development environments -- quo vadis?
News & Analysis  
8/11/2006   Post a comment
The electronics industry is at risk of not being able to deliver the next generation of consumer devices, writes EDA veteran and Imperas CEO Simon Davidmann.
Roundup of Agilent FPGA debugging articles using cores
Design How-To  
8/10/2006   Post a comment
By popular demand, here's a roundup of the popular series of four "How To" articles by Brad Frieden of Agilent describing how to use cores to debug FPGA designs.
Aided by locale, DAC attendance jumps 25 percent
News & Analysis  
8/10/2006   Post a comment
The 43rd Design Automation Conference here last month drew 6,875 general conference and exhibit attendees, up 25 percent from 5,505 general attendees in 2005, DAC organizers said.
Graphical design and 'domain experts' a good fit
News & Analysis  
8/10/2006   Post a comment
Drag-and-drop programming techniques and graphical user interfaces are needed to overcome the "experts-need-only-apply" mentality that now prevails in electronics system design, according to panelists at a National Instruments event.
How to accelerate algorithms by automatically generating FPGA coprocessors
Design How-To  
8/9/2006   Post a comment
Recent advances in C-to-FPGA design methodologies and tools facilitate the rapid creation of hardware-accelerated embedded systems.
VHDL, Verilog models available for Spansion flash
Product News  
8/8/2006   Post a comment
Free Model Foundry, an open source model warehouse and design services company promoting development and distribution of simulation models of electronic components, announced the development of VHDL and Verilog models for Spansion's MirrorBit Ornandt devices.
Revision moves LabView 'deeper into Mathworks territory'
Product News  
8/8/2006   Post a comment
National Instruments observed the 20th anniversary of LabView with a new release that incorporates features observers said move the tool deeper into The Mathworks' territory and could open doors for LabView in the modeling and system development portion of the tool market.
Dongbu develops design kits for high-voltage chips
Product News  
8/8/2006   Post a comment
Dongbu Electronics Co. Ltd., a South Korean pure-play semiconductor foundry, said Tuesday (Aug. 8) it has completed development of process design kits (PDKs) for high-voltage semiconductor devices in collaboration with EDA market leader Cadence Design Systems Inc.
Page 1 / 2   >   >>


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Creating a Vetinari Clock Using Antique Analog Meters
Max Maxfield
58 comments
As you may recall, the Mighty Hamster (a.k.a. Mike Field) graced my humble office with a visit a couple of weeks ago. (See All Hail the Mighty Hamster.) While he was here, Hamster noticed ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
11 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
11 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
45 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)