FPGA-to-ASIC conversion with zero NRE Blog 8/31/2010 10 comments KaiSemi performs automated FPGA-to-ASIC conversion with Zero NRE, functional guarantee, and a very short cycle time; this is a full turnkey solution that is seamless to the customer.
Enhancing robust SEU mitigation with 28-nm FPGAs Design How-To 8/17/2010 Post a comment Systems designed with FPGAs benefit from significant improvements over ASICS, such as
rapid-process technology scaling and design innovation, which permit the use of FPGAs in
high-availability, high-reliability, and safety-critical systems. However, along with
technology scaling come other effects such as increased susceptibility to soft errors that
previously could be ignored. These soft errors, caused by single event upsets (SEUs), are
nondestructive and can be corrected without syst
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.