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posted in August 2010
Avnet and Actel offer great SmartFusion mixed-signal FPGA workshops
Blog  
8/31/2010   6 comments
Avnet Memec and Actel are hosting a series of one-day workshop that provide hands-on experience working with Actel's SmartFusion mixed-signal FPGAs and design tools.
FPGA-to-ASIC conversion with zero NRE
Blog  
8/31/2010   10 comments
KaiSemi performs automated FPGA-to-ASIC conversion with Zero NRE, functional guarantee, and a very short cycle time; this is a full turnkey solution that is seamless to the customer.
Optimizing the manufacturing test program, data collection, and diagnosis for yield analysis
Design How-To  
8/29/2010   Post a comment
Engineers can get the most value out of IC failure diagnosis by implementing certain best practices. This article describes how to organize a test program for optimal data collection and how to optimize the data collection process to achieve yield learning goals.
Enhancing robust SEU mitigation with 28-nm FPGAs
Design How-To  
8/17/2010   Post a comment
Systems designed with FPGAs benefit from significant improvements over ASICS, such as rapid-process technology scaling and design innovation, which permit the use of FPGAs in high-availability, high-reliability, and safety-critical systems. However, along with technology scaling come other effects such as increased susceptibility to soft errors that previously could be ignored. These soft errors, caused by single event upsets (SEUs), are nondestructive and can be corrected without syst


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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