FPGA-to-ASIC conversion with zero NRE Blog 8/31/2010 10 comments KaiSemi performs automated FPGA-to-ASIC conversion with Zero NRE, functional guarantee, and a very short cycle time; this is a full turnkey solution that is seamless to the customer.
Enhancing robust SEU mitigation with 28-nm FPGAs Design How-To 8/17/2010 Post a comment Systems designed with FPGAs benefit from significant improvements over ASICS, such as
rapid-process technology scaling and design innovation, which permit the use of FPGAs in
high-availability, high-reliability, and safety-critical systems. However, along with
technology scaling come other effects such as increased susceptibility to soft errors that
previously could be ignored. These soft errors, caused by single event upsets (SEUs), are
nondestructive and can be corrected without syst
In conjunction with unveiling of EE Times’ Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. One of Silicon Valley's great contributions to the world has been the demonstration of how the application of entrepreneurship and venture capital to electronics and semiconductor hardware can create wealth with developments in semiconductors, displays, design automation, MEMS and across the breadth of hardware developments. But in recent years concerns have been raised that traditional venture capital has turned its back on hardware-related startups in favor of software and Internet applications and services. Panelists from incubators join Peter Clarke in debate.