Breaking News
Content tagged with Design Tools (EDA)
posted in August 2012
Page 1 / 2   >   >>
What were they thinking: backups and patents
Blog  
8/31/2012   4 comments
Do you know what patent #1 was about? Surprise there are two of them...
Best of the web – August 31st
Blog  
8/31/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
Xilinx to demo broadcast innovation and differentiation at IBC 2012
Product News  
8/30/2012   Post a comment
Broadcast engineers are faced with the challenges of providing cost-effective, high performance video, audio, and network systems.
Avnet Wi-Fi dev kit designed to attach to FPGA dev boards
Product News  
8/30/2012   5 comments
Avnet Electronics Marketing Americas Introduces the CC3000-Pmod Compatible Wi-Fi Adapter Kit.
Seriously?
Programmable Logic DesignLine Blog  
8/29/2012   11 comments
My knee-jerk reaction was "Oh dear, what have I said or done that has raised my friend's ire?"
EDA/IP Weekly Roundup – August 29th
Blog  
8/29/2012   Post a comment
Sonics, Intel, IMS, TSMC, Amkor, Bluetooth, Samsung, ASML, ARM, Synopsys, Altera, Xilinx, Delft, Open-Silicon and Evatronix made the lineup today. See here for their news…
Collaborative Advantage: How Apple-Samsung will impact standards development
Blog  
8/29/2012   11 comments
The significant and relevant impact of this lawsuit on the development and adoption of standards has been widely overlooked...
OpenCL for FPGAs previewed via Altera's early access program
Product News  
8/28/2012   Post a comment
Customers receive a first look at how OpenCL can simplify FPGA development and increase productivity.
Xilinx acquires embedded Linux provider PetaLogix
Product News  
8/28/2012   Post a comment
The acquisition of the original developer of embedded Linux solutions for Xilinx FPGAs further strengthens Xilinx's All Programmable solutions for SoC designs.
Promo pricing for new Lattice iCEblink40 eval kits
Product News  
8/28/2012   1 comment
New iCEblink40 evaluation kits from Lattice Semiconductor accelerate application development for the low-cost, low-power iCE40 mobileFPGA family.
How Ford engineers cut costs and prototypes with CAE
Design How-To  
8/28/2012   Post a comment
Adopting CAE analysis tools has helped Ford to cut the number of physical prototypes it uses, reduce costs, and improve quality. Asaad Makki, Global Electrical CAE Supervisor, and Dave Beard, Senior CAE Engineer, explain their approach.
FLIR speeds thermal imaging FPGA development
Product News  
8/28/2012   3 comments
Automatic HDL generation from MATLAB reduces concept to field-testable prototype development time by 60%.
Opinion: Integrating power electronics design technologies
Blog  
8/28/2012   Post a comment
The need to supply, modify and control the voltage, current or frequency of electric power creates some considerable challenges…
Hurray! Xilinx outperforms Spacely Space Sprockets
Programmable Logic DesignLine Blog  
8/27/2012   3 comments
Spacely Space Sprockets came in at number 25 of the twenty-five largest fictional companies in history with 2007 revenues of $1.3 billion.
DoCD – DCD’s on-Chip FPGA/SoC Debugger
Product News  
8/27/2012   Post a comment
DoCD offers real time, non-intrusive debug capability, enabling pre-silicon validation and post-silicon on-chip software debugging.
Layer-aware optimization
Design How-To  
8/27/2012   Post a comment
Layer-aware optimization is a necessity at 28nm and below to better predict system performance and ensure efficient design closure...
Finally, a hardware accelerator: Bolt's Ben Einstein on a leg up for startups
News & Analysis  
8/27/2012   5 comments
Product designer and entrepreneur Ben Einstein (shown) is part of a team in Boston looking to give hardware startups their fair share of the glory.
Mentor riding 28-nm transition wave
News & Analysis  
8/24/2012   3 comments
Mentor Graphics CEO Walden Rhines (shown) said Mentor and other EDA vendors are benefiting from customers' transition to more advanced design nodes.
What were they thinking: sock wedgie
Blog  
8/24/2012   6 comments
On Fridays, I love to find some humor for the week, and patents are often a source of inspiration. Here is one I found for a problem I didn’t know existed – a sock wedgie…
Startup spotlight: Verifyter
Blog  
8/24/2012   Post a comment
I always love it when I get to learn about a new company, a start-up with a vision for the future, something that hasn’t been tried before…
Best of the web – August 24th
Blog  
8/24/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
ASSET releases IJTAG tutorial
Blog  
8/23/2012   4 comments
IJTAG could bring some standardization to the usage of on-chip instrumentation, a move that will help make this a much easier task in SoC design…
Zorian of Synopsys to head 50th DAC planning
News & Analysis  
8/23/2012   2 comments
Planning for the 50th Design Automation Conference has begun with the naming of the executive committee to be chaired by Yervant Zorian (shown), chief architect at Synopsys.
Synopsys raises profit target again after strong quarter
News & Analysis  
8/22/2012   Post a comment
EDA and IP vendor Synopsys raised its profitability target for its current fiscal year for a second consecutive quarter after reporting sales in line with expectations and profitability that exceeded analysts' estimates for the quarter ended last month.
Cheesy Sci-Fi TV Series of the 60s and 70s
Programmable Logic DesignLine Blog  
8/22/2012   90 comments
Here are some of the cheesy Sci-Fi TV Series I used to watch in the 60s and 70s. Did you see these? If so, which did you like the best (and which did you hate the most)?
EDA/IP Weekly Roundup – August 22nd
Blog  
8/22/2012   Post a comment
ASSET, Synopsys, Sidense, Kilopass, Cypress, Mentor, EVE, Arteris and Avery made the lineup today. See here for their news…
Cypress tips upgraded IDE for PSoC
Product News  
8/21/2012   Post a comment
Cypress Semiconductor rolled out a new version of the PSoC 3 and PSoC 5 programmable system-on-chip development environment with more than 100 new features and enhancements.
Book excerpt: Introduction to Open Core Protocol Part 3
Blog  
8/21/2012   Post a comment
The Open Core Protocol (OCP) is designed to accelerate IP core-to-core interface design efforts and this book is designed to bring you up to speed faster…
Fixing an Atmospheric Monitor
Design How-To  
8/20/2012   19 comments
Max recently sent me his latest (non-working) project -- an Atmospherics Monitor. Here is the tale of the reawakening of this unit.
Design workflow management enhances SoC design quality and efficiency
Design How-To  
8/20/2012   5 comments
To meet aggressive design schedules while ensuring the design quality, companies should have a flow and data management system…
The worst is behind you…
Programmable Logic DesignLine Blog  
8/20/2012   19 comments
Is the worst behind you? Or can you think of something that is even more cringe-inducing?
What were they thinking: Apple, Google, Oracle and Samsung dueling
Blog  
8/17/2012   11 comments
The technology dueling continues between Apple, Samsung, Google and Oracle. Will anyone win...
Best of the Web, August 17
Blog  
8/17/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
Three students named winners of Synopsys optical design award
News & Analysis  
8/16/2012   Post a comment
Synopsys announced that two students from the University of Rochester and one from the University of Alabama-Huntsville are the winners of the 2012 Robert S. Hilbert Memorial Optical Design Competition.
Opinion: Security is the Achilles heel
Engineering Investigations  
8/16/2012   9 comments
One of the first changes that must occur is in the way Internet of Things System-on-Chip devices are designed and manufactured…
How to simulate cable in SPICE
Design How-To  
8/15/2012   1 comment
This article discusses the two main loss effects related to cables (the skin effect and dielectric losses) and presents a simple method for modeling the cable for use in standard SPICE simulators.
Using MISRA C and C++ for security and reliability. Part II
Design How-To  
8/15/2012   Post a comment
After introducing MISRA C and MISRA C++ and presenting the taxonomy of rules in Part One, Compiler Development reviews here the rules mentioned in Part One.
EDA/IP Weekly Roundup – August 15th
Blog  
8/15/2012   Post a comment
ARM, Cadence, Globalfoundries, Verific and Aldec made the lineup today. See here for their news…
TI's 32-bit C2000 Piccolo F2802x microcontrollers
Product News  
8/13/2012   3 comments
32-bit microcontrollers feature integration in small packages and robust hardware and software ecosystems to ease development for white goods and industrial applications.
Microchip expands serial SRAM lineup
Product News  
8/13/2012   Post a comment
Also debuts non-volatile, battery-backed serial SRAMs at significantly lower cost than any other non-volatile SRAM, FRAM, or parallel SRAM.
The forgotten SoC verification team
Design How-To  
8/13/2012   4 comments
There is a growing class of verification engineers who are woefully under-appreciated in terms of the complexity of the job they have to do and the lack of tools made available to them…
Best of the web – August 10th
Blog  
8/11/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
What were they thinking: a use for body piercing
Blog  
8/11/2012   6 comments
Body piercing has always been a strange thing to do to me, but now I find that they may have a real application. Hmmm. Still don’t think I am going to get those studs…
"TGIF" said Max, happily!
Programmable Logic DesignLine Blog  
8/10/2012   10 comments
Good Grief! What a week it's been…
ARM continues Synopsys EDA support
News & Analysis  
8/10/2012   1 comment
Processor IP licensor ARM has said it continues to work with all the major EDA companies after being asked about claimed improvements in the design of ARM-based system-chips made using design tools from Cadence.
Wafer-scale CMOS X-ray imaging for medical apps
Design How-To  
8/10/2012   Post a comment
There is a growing interest in the use of solid-state based X-ray medical imaging and detection systems in the replacement of conventional diagnostic imaging techniques. One of these technologies is wafer-scale CMOS sensor-based imaging, which can bring advantages in terms of performance such as high resolution, high dynamic range and low noise capabilities.
London Calling: Deutsche does M2M
Blog  
8/10/2012   3 comments
Software development is a fast moving business. Before the Qt development framework is fully established Nokia has had to sell it on and the lure of the Internet of Things is exciting Deutsche Telekom.
Terasic, Altera FPGA-based boards for high-frequency trading
Product News  
8/9/2012   1 comment
Terasic to release new Altera Stratix V FPGA-based boards for high-frequency trading and cloud computing applications.
There's punography everywhere!
Blog  
8/9/2012   43 comments
It seems that everywhere you turn these days you run into more punography, but what can we do about it?
Microelectronics Olympiad backed by Synopsys, IEEE
News & Analysis  
8/9/2012   Post a comment
It won't be speed over 100-meters but knowledge about microelectronics at the nanometer-scale that will determine the winners in a competition to take place in Yerevan, the capital of Armenia, later this year. The idea behind the design games is to turn microelectronics engineers into medal winners and inspire the next generation to enter the electronics industry.
Page 1 / 2   >   >>


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Steve Wozniak Reacts to Latest iPhone
Max Maxfield
1 Comment
Funnily enough, just a few days ago as I pen these words, I was chatting with my wife (Gina the Gorgeous) when she informed me that -- as a kid -- she had never played at making a ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)