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Content tagged with Design Tools (EDA)
posted in August 2012
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ARM, Cadence tune support for processor design
News & Analysis  
8/9/2012   2 comments
Processor IP licensor ARM and EDA software vendor Cadence have said they have been working together to link ARM's processor optimization packages to Cadence's software for digital design called Encounter.
Have you got the (inside) edge?
Product News  
8/8/2012   Post a comment
I just received my copy of Altera's monthly eNewsletter – Inside Edge. On the off-chance you haven't already signed up for this, the highlights are as follows…
Xilinx takes Zynq-7000 All Programmable SoC to 1 GHz
Product News  
8/8/2012   1 comment
New performance benchmarks and smaller form factor packaging for All Programmable SoC family.
LabVIEW FPGA innovation award
News & Analysis  
8/8/2012   Post a comment
Xilinx honors NI LabVIEW FPGA innovation award winner at NIWeek graphical system design achievement awards ceremony.
Using MISRA C and C++ for security and reliability
Design How-To  
8/8/2012   3 comments
Even the most well thought-out design is vulnerable to flaws when the implementation falls short of the design. This paper focuses on how one can use a set of coding guidelines, called MISRA C and MISRA C++, to help root out bugs introduced during the coding stage.
EDA/IP Weekly Roundup – August 8th
Blog  
8/8/2012   Post a comment
Synopsys, Renesas, TSMC, ASML, ARM, Kilopass, ASSET InterTech and Mentor made the lineup today. See here for their news…
Character traits of a CEO
Blog  
8/8/2012   Post a comment
A CEO who thinks that he or she has all the answers is a recipe for disaster.
Don't fall in the… arrggghhh!!!
Programmable Logic DesignLine Blog  
8/7/2012   13 comments
I just saw a couple of very interesting pictures. I'm not sure if they are real or not…
The basics of FPGA mathematics
Design How-To  
8/7/2012   13 comments
One of the main advantages of the FPGA is its ability to perform mathematical functions as desired. Here's a refresher on the basic rules and methods involved.
Book excerpt: Introduction to Open Core Protocol
Blog  
8/7/2012   2 comments
The Open Core Protocol (OCP) is designed to accelerate IP core-to-core interface design efforts and this book is designed to bring you up to speed faster…
What's new in automotive electronics (August 6, 2012)
Blog  
8/6/2012   Post a comment
A selection of automotive electronics stories from around the web and the EE Times/UBM Electronics network from recent days
Digital Core Design introduces DMAC-RMII
Product News  
8/6/2012   Post a comment
This IP Core, for use in ASICs/SoCs and FPGAs, supports 10BASE-T and 100BASE-TX/FX IEEE 802.3-2002 compliant RMII PHYs.
Xilinx spotlights All Programmable Technology at NIWeek 2012
News & Analysis  
8/6/2012   Post a comment
The folks at Xilinx have announced their participation at NIWeek 2012, booth #618, August 6-9, 2012 at the Austin Convention Center.
Requirements Traceability design how-to
Design How-To  
8/6/2012   9 comments
The majority of defects in embedded software space are still requirements related. How do design engineers overcome this problem?
Designing a robust clock tree structure
Design How-To  
8/6/2012   Post a comment
With technology advancement, clock tree robustness has become an even more critical factor affecting SoC performance. However, designing a symmetrical clock tree with minimum latency and skew is not enough…
Empowering your hardware engineers
Design How-To  
8/5/2012   12 comments
Never lose sleep over a new embedded hardware design again…
A different perspective on life
Blog  
8/4/2012   6 comments
We create things from sand, as do the monks from Drepung Loseling Phukhang Monastery, but the results are very different...
Littelfuse's Thane Parker amps up circuit protection
Blog  
8/3/2012   1 comment
Life ain't always easy for today’s design engineers. Pressured by the ever quicker cycle turnarounds for new products, engineers who once had months of multiple attempts to get a design right are finding their window of test opportunities squeezed. But that doesn’t mean they can simply cut corners.
What's the dress code where you work?
Programmable Logic DesignLine Blog  
8/3/2012   71 comments
I stopped at the gas station on the way into work the other day to grab a cup of coffee. As I was leaving, a guy about my age was entering. Together we provided quite a contrast…
What were they thinking: America’s top colleges
Blog  
8/3/2012   2 comments
Forbes publishes their top American college list and I don't believe a word of it. I rename it the top ego list...
Best of the web – August 3rd
Blog  
8/3/2012   Post a comment
Blogs from around the web that made my “best of the web” list this week…
Synopsys acquires Springsoft – thesis dead
Blog  
8/3/2012   Post a comment
My emerging middle class thesis within EDA appears to be dead. Will Synopsys get indigestion...
Is Synopsys helping chip making return to its roots?
Blog  
8/3/2012   8 comments
The news that Synopsys wants to bring together the R&D teams and EDA software products from its recent and proposed acquisitions of Magma, Ciranova and SpringSoft puts me in mind of an intriguing and market-changing perspective.
Synopsys to buy SpringSoft for $406 million
News & Analysis  
8/3/2012   6 comments
EDA software leader Synopsys has agreed to purchase Taiwanese IC debug and verification software company SpringSoft for $406 million, or approximately $305 million net of cash acquired.
Multicore 'string processor' firm sold to Ericsson
News & Analysis  
8/3/2012   Post a comment
Aspex Semiconductor, a vendor of parallel processing accelerator boards, has been sold to Ericsson AB for an undisclosed sum.
Netlist claims to accelerate EDA applications by 8%
Product News  
8/2/2012   4 comments
Can a simple server upgrade improve the performance of your EDA applications? Netlist has a new memory module that they believe can deliver…
The adventures of a Sherlock Homes "wannabe"
Blog  
8/2/2012   4 comments
In which one of our readers turns into an amateur sleuth, tracks down the doer of a dastardly deed, and ensures that the scales of justice are balanced.
How social media tools can change the EDA space for the better
Blog  
8/1/2012   3 comments
How important is social media within EDA? One opinion is that you cannot do business without it and those that try and leaving a lot on the table…
Live webinar on motor control apps with FPGAs
Product News  
8/1/2012   2 comments
I just heard from those nice folks at Microsemi that they are hosting a Free Webinar on August 28 2012 (8:00am to 9:00am Pacific Time).
NI LabVIEW uses HLS to improve FPGA design productivity
Product News  
8/1/2012   1 comment
The new LabVIEW FPGA IP Builder software from National Instruments incorporates high-level synthesis (HLS) technology to accelerate system design through increased abstraction.
New sim, testing tools used to design Mars lander
News & Analysis  
8/1/2012   11 comments
A toolbox supplied by a Siemens software unit was used to simulate the thermal loads and G-forces to be encountered by the Mars Science Laboratory spacecraft as it attempts a risky landing of the Curiosity rover on the Red Planet.
Shakespearian version of the Hokey Pokey
Programmable Logic DesignLine Blog  
8/1/2012   18 comments
To be honest, this is one of those songs you are brought up with and never really think about. I remember the big family Christmas parties when I was a kid...
EDA/IP Weekly Roundup – August 1st
Blog  
8/1/2012   Post a comment
Xilinx, Oski, Synopsys, Ciranova, Newark element14 and Calypto made the lineup today. See here for their news…
Book review: Empower your inner manager
Blog  
8/1/2012   Post a comment
A new management book written by one of our own entrepreneurs will help you plot a course for self-improvement…
Time to streamline thermal management design and production
Design How-To  
8/1/2012   1 comment
A major issue that tends to delay a product’s introduction to the marketplace is the occasional lack of communication between designers and manufacturers. One reason is that the two entities may be scattered either across the country or the globe. Results show that placing the entities under one roof helps improve quality and completion time with less likelihood of problems after the market introduction.
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