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posted in September 2003
Maximize your utilization of acceleration and emulation
News & Analysis  
9/26/2003   Post a comment
Emulation and acceleration hardware is a huge investment, so you want to maximize your usage. Cadence Design Systems' Ray Turner explains various kinds of resource sharing that make these tools available to multiple team members.
Selecting PLLs for ASIC Applications requires tradeoffs
News & Analysis  
9/25/2003   Post a comment
PLLs, like many other analog IP macros, come with many features and specifications. Selecting the correct PLL early in the design can help the design team make tradeoffs when they are less costly, improve the integration quality of the PLL, and avoid surprises close to tapeout. From the September PA magazine folio, a True Circuits expert gives this assessment of what you should look for.
System-In-Package or System-On-Chip?
News & Analysis  
9/19/2003   Post a comment
System-in-package (SiP) has created a new set of design challenges. SiP designs are typically only attempted when a wall is reached-such as size or performance constraints-and conventional system-on-chip (SoC) solutions are too expensive to implement.
Modeling challenges for 90 nm and below
News & Analysis  
9/19/2003   Post a comment
Based on a series of physical effects, CMOS is showing increasing design challenges at 90 nanometers and below.
Scaling down on the wings of a FinFET-DGCMOS
News & Analysis  
9/19/2003   Post a comment
The double-gate (DG) FET provides a fundamental advantage over conventional single-gate (SG) FETs.
Embedding software in the SoC World
News & Analysis  
9/19/2003   Post a comment
The semiconductor industry continues to follow Moore's Law, doubling the complexity of ICs every 18 months, to the point where it will soon be able to manufacture chips with 100 million gates.
Packaging designs for radio-frequency ICs
Design How-To  
9/19/2003   Post a comment
The performance of a radio-frequency integrated circuit can be dramatically affected by the package environment, yet packaging technology has received comparatively little attention compared with IC fabrication technology or RF IC design.
Chalcogenide memory looks promising
News & Analysis  
9/19/2003   Post a comment
Chalcogenide RAM, made of the Ge2Sb2Te5 materials, has recently been regarded as the most promising next-generation memory.
Transceiver design is fully integrated
News & Analysis  
9/19/2003   Post a comment
In this article, we describe a 10.5-Gbit/second to 13.5-Gbit/s transceiver in a 0.13-micron CMOS technology.
Declarative programming language simplifies hardware design
Design How-To  
9/18/2003   Post a comment
Confluence is a declarative, functional programming language that makes it easy to describe complex hardware. It then compiles into an HDL. In this overview, Confluence creator Tom Hawkins shows how the language can describe a parametric FIR filter in 23 lines of code.
Rethinking test at 130 nanometers and below
News & Analysis  
9/12/2003   Post a comment
Design-for-test techniques need an overhaul, according to Mentor Graphics engineer Scott Cook. In this article, he discusses the need for at-speed testing, new fault types, and embedded test solutions.
For the engineer's toolbox: Simulation Program with Integrated Circuit Emphasis
Blog  
9/10/2003   Post a comment
Most, if not all of the manufacturers of analog ICs will provide, at no charge, a library of Spice models of many of their linear ICs except the Spice model is not the real world. Our applications guru in Tucson wonders where he might challenge the authority of this universal modeler. Join Bill Klein for the latest installment of his series, "A call I took last week."
Programmable Logic Devices offer co processor muscle for high bandwidth image processing " Part 1
News & Analysis  
9/10/2003   Post a comment
In medical imaging applications, such as Computed Tomography and Magnetic Resonance Imaging, the input data is not a stream of successive bytes, but rather it is a large data block (an image) residing in memory or on disk. The task of the image processing chain is typically to tile the image into sub-blocks, perform a series of linear algebraic transforms on those blocks, and place the resultant data back on the disk. In this two-part series, an Altera engineers offers insights on using programm
Programmable Logic Devices offer co processor muscle for high bandwidth image processing " Part 2
News & Analysis  
9/9/2003   Post a comment
In medical imaging applications, such as Computed Tomography and Magnetic Resonance Imaging, the input data is not a stream of successive bytes, but rather it is a large data block (an image) residing in memory or on disk. The task of the image processing chain is typically to tile the image into sub-blocks, perform a series of linear algebraic transforms on those blocks, and place the resultant data back on the disk. In the second part of this series, an Altera engineers offers on configuring a
QualCore gains analog IP and designers in LEDA acquisition
News & Analysis  
9/9/2003   Post a comment
Digital design services and IP company QualCore Logic Inc. has acquired analog and mixed-signal design core vendor LEDA Systems Inc. (Plano, Texas) for an undisclosed amount. Mahendra Jain, president of QualCore Logic, was excited. Mike Santarini was there to catch his enthusiasm.
Write your own PCB design rule checker
Design How-To  
9/5/2003   Post a comment
You don't have to rely on your EDA vendor's PCB design rule checker (DRC). In this tutorial, Intel engineer Luke Chang shows you how to write one that meets your specific requirements, and does a lot more than just DRC.
Analyzing inductive noise in power grids
News & Analysis  
9/4/2003   Post a comment
In any chip design, large, rapidly changing currents in a circuit block can cause large inductive voltage changes in a low resistance power grid. These voltage changes propagate across the chip with very little attenuation causing timing errors, increased stress in thin gate oxides and, in extreme cases, complete circuit failure. This article from eeDesign.com, by a device physicist and simulation expert, provides designers with an overview of the techniques needed to analyze resistive, inductiv
Gurus urge IC design overhaul
News & Analysis  
9/2/2003   Post a comment


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15 comments
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46 comments
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