Oasis file format gets endorsed by DFM startup News & Analysis 9/30/2005 Post a comment Oasis Tooling is expected to announce next week that Aprio Technologies is the first commercial licensee of Oasis test cases and tools to assist in the development and optimization of Oasis database technology for photomask layout exchange and interchange.
India's TCS launches R&D lab for emerging technologies News & Analysis 9/29/2005 Post a comment India’s largest software services company, Tata Consultancy Services, has opened an R&D facility in New Delhi to focus on emerging technologies that could drive disruptive change in the global technology industry and develop re-usable frameworks using these.
Yogitech offering mixed-signal verification kit Product News 9/29/2005 Post a comment Yogitech introduced an integrated, automated verification component kit that the company claims that goes beyond the limits of traditional mixed-signal verification solutions to drastically reduce verification time and increase quality.
Cypress rolls out zero-delay buffers News & Analysis 9/29/2005 Post a comment Cypress Semiconductor announced the production availability of enhanced performance zero-delay buffers, which Cypress claims outperform pin-compatible products for high-speed communications and consumer devices.
Forte beefs up behavioral synthesis tool News & Analysis 9/27/2005 Post a comment Forte is rolling out an upgraded version of its Cynthesizer SystemC-based behavioral synthesis tool with new capabilities said to further ease the adoption of electronic system-level design.
Power.org adds eight members News & Analysis 9/27/2005 Post a comment Power.org, an open community developing standards and applications around IBM Corp.'s Power Architecture, announced Monday that eight new members have joined the organization, bring total membership to more than 30 companies.
SystemVerilog verification manual published News & Analysis 9/21/2005 Post a comment The SystemVerilog Verification Methodology Manual, a book authored by verification experts from Synopsys and ARM describing the use of SystemVerilog for verification, has been publish by Springer Science + Business Media.
'Common platform' partners to collaborate on DFM News & Analysis 9/21/2005 Post a comment IBM, Chartered Semiconductor and Samsung Electronics announced a collaborative design-for-manufacturing initiative that will offer a series of rules, models and utility kits for increasing manufacturing predictability, control and yield.
Legend Design releases multiprocessing simulation manager News & Analysis 9/20/2005 Post a comment Legend Design Technology released the CharFlo-MonteCarlo! simulation manager for multiprocessing statistical circuit simulation, which is bundled with the company's MSIM application program interface (API). The bundled product enables designers to examine the impacts of statistical Spice models and enhance designs for yield, according to the company.
ESL design group float set to raise $18 million News & Analysis 9/19/2005 Post a comment Electronic system level (ESL) design and synthesis vendor Celoxica plc is planning to float on the London Alternative Investment Market and expects to raise £10 million ($18 million), valuing the company at about £25 million ($45 million).
Analysts give thumbs up to CDNLive! News & Analysis 9/16/2005 Post a comment The announcements were not necessarily news, but EDA analysts expressed support for the new marketing tactics and technologies rolled out this week at Cadence Design Systems' user conference.
Madhavan stresses need for automation News & Analysis 9/15/2005 Post a comment The term "EDA" is coming to stand for "electronic design assistance," according to Magma Design Automation Inc.'s Rajeev Madhavan, who warned that design tool vendors must provide more automation in order to extract greater value from customers.
Si2 forms Open Modeling Coalition News & Analysis 9/14/2005 Post a comment Si2 Wednesday launched a new coalition, modeling after the OpenAccess Coalition, to address critical issues in the characterization and modeling of libraries and intellectual property.
Fister 'passionate' about kits News & Analysis 9/13/2005 Post a comment Cadence Design Systems President and CEO Michael Fister kicked off the CDNLive! designer network conference Monday by extolling the virtues of the company's new methodology kits.
Indian researchers propose new SoC test method News & Analysis 9/12/2005 Post a comment With efficient test access architecture of much interest to the SoC design and test community, two researchers at an Indian technical institute have proposed a design-for-test method for digital SoC designs using a Test Access Mechanism (TAM) switch.
Cadence speeds IC physical verification Product News 9/12/2005 Post a comment Promising a "massively parallel" approach to IC design rule checking and layout-versus-schematic, Cadence Design Systems is rolling out its Physical Verification System for designs at 90 nm and below.
Blog Doing Math in FPGAs Tom Burke 15 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...