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posted in September 2005
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File viewer adds EDA enhancements
News & Analysis  
9/30/2005   Post a comment
Cimmetry Systems Corp. has released version 19 of the company's AutoVue enterprise-wide file viewing software.
Oasis file format gets endorsed by DFM startup
News & Analysis  
9/30/2005   Post a comment
Oasis Tooling is expected to announce next week that Aprio Technologies is the first commercial licensee of Oasis test cases and tools to assist in the development and optimization of Oasis database technology for photomask layout exchange and interchange.
CriticalBlue supporting Power architecture with Cascade
News & Analysis  
9/30/2005   Post a comment
Embedded systems design tool startup CriticalBlue has added support for IBM's Power architecture to its Cascade co-processor synthesis tool
Startup to develop litho process window apps with Crolles2
News & Analysis  
9/30/2005   Post a comment
Startup Brion Technologies has signed a joint development agreement with the partners in the Crolles2 R&D alliance.
India's TCS launches R&D lab for emerging technologies
News & Analysis  
9/29/2005   Post a comment
India’s largest software services company, Tata Consultancy Services, has opened an R&D facility in New Delhi to focus on emerging technologies that could drive disruptive change in the global technology industry and develop re-usable frameworks using these.
Yogitech offering mixed-signal verification kit
Product News  
9/29/2005   Post a comment
Yogitech introduced an integrated, automated verification component kit that the company claims that goes beyond the limits of traditional mixed-signal verification solutions to drastically reduce verification time and increase quality.
Cypress rolls out zero-delay buffers
News & Analysis  
9/29/2005   Post a comment
Cypress Semiconductor announced the production availability of enhanced performance zero-delay buffers, which Cypress claims outperform pin-compatible products for high-speed communications and consumer devices.
IEEE approves Property Specification Language standard
News & Analysis  
9/28/2005   Post a comment
In what may be record time for the IEEE standardization process, the organization has approved the standard for Property Specification Language for the verification of complex software.
EDA Consortium issues call for DAC papers
News & Analysis  
9/28/2005   Post a comment
The Electronic Design Automation Consortium has issed a call for industry contributions to the 2006 Design Automation Conference technical program.
Synopsys files two additional suits against Magma
News & Analysis  
9/28/2005   Post a comment
Synopsys has filed two additional lawsuits in its high-profile patent dispute with Magma Design Automation.
Denali, LSI Logic ink agreement on memory interface IP
News & Analysis  
9/27/2005   Post a comment
Denali Software and LSI Logic have entered into a strategic agreement on memory interface intellectual property, the companies said.
Synopsys moving to acquire HPL Technologies
News & Analysis  
9/27/2005   Post a comment
Synopsys has initiated discussions with yield optimization technology provider HPL Technologiesabout the possibility of acquiring the company, according to a regulatory filing.
CEOs don't think EDA will be hurt by gas prices, says analyst
News & Analysis  
9/27/2005   Post a comment
EDA chief executives believe that the industry is too far removed from consumer spending to be impacted by recent gas prices increases, according to the results of an informal CEO survey conducted by RBC Capital Markets.
Synfora creating tighter integration to Novas tools
News & Analysis  
9/27/2005   Post a comment
Synfora has joined the Novas Harmony Program and plans to tightly integrate its Pico software for application engine synthesis with Novas Software's Verdi automated debug system and nLint module.
Forte beefs up behavioral synthesis tool
News & Analysis  
9/27/2005   Post a comment
Forte is rolling out an upgraded version of its Cynthesizer SystemC-based behavioral synthesis tool with new capabilities said to further ease the adoption of electronic system-level design.
Power.org adds eight members
News & Analysis  
9/27/2005   Post a comment
Power.org, an open community developing standards and applications around IBM Corp.'s Power Architecture, announced Monday that eight new members have joined the organization, bring total membership to more than 30 companies.
Cadence offering custom-synthesized approach to PowerPC
News & Analysis  
9/26/2005   Post a comment
Cadence Design Systems introduced a comprehensive set of services for system-on-chip designers embedding PowerPC cores, including silicon validation of a new custom-synthesized design approach.
Sequence Design introduces 'formal' power grid verification
News & Analysis  
9/26/2005   Post a comment
Sequence Design this week is rolling out a new product focused on IC power grid integrity.
On-chip instrumentation aids OCP debugging
Design How-To  
9/26/2005   Post a comment
On-chip instrumentation uses silicon IP to provide real-time visibility into systems that use the OCP bus protocol. Neal Stollon of First Silicon Solutions explains how it works.
ST, Synopsys demonstrate SATA IP compatibility for 90 nm
News & Analysis  
9/23/2005   Post a comment
STMicroelectronics and Synopsys announced that they are working together to conduct Serial ATA interoperability testing using ST's 90-nanometer Multi-Interface PHY and Synopsys' DesignWare SATA host controller intellectual property core.
'Common platform' partners tight-lipped on DFM vendors
News & Analysis  
9/22/2005   Post a comment
The partnership between IBM, Chartered and Samsung announced an initiative on design-for-manufacturing earlier this week, but the companies are keeping quiet about which vendors are participating.
SoftJin offering GDSII file compression technology
News & Analysis  
9/22/2005   Post a comment
India’s SoftJin has announced a GDSII compression technology, GDSIIZIP, that it claims compresses the files by up to 20 times.
SystemVerilog verification manual published
News & Analysis  
9/21/2005   Post a comment
The SystemVerilog Verification Methodology Manual, a book authored by verification experts from Synopsys and ARM describing the use of SystemVerilog for verification, has been publish by Springer Science + Business Media.
CoWare, MIPS recognized for contributions to OCP-IP
News & Analysis  
9/21/2005   Post a comment
Open Core Protocol International Partnership has named CoWare and MIPS Technologies joint winners of its 2005 Outstanding Contributor of the Year Award.
'Common platform' partners to collaborate on DFM
News & Analysis  
9/21/2005   Post a comment
IBM, Chartered Semiconductor and Samsung Electronics announced a collaborative design-for-manufacturing initiative that will offer a series of rules, models and utility kits for increasing manufacturing predictability, control and yield.
Knowlent joins VSIA standards body
News & Analysis  
9/20/2005   Post a comment
Intellectual property/EDA vendor Knowlent Corp. has joined the VSI Alliance IP and system-on-chip standards body.
Mentor names new VP/treasurer
News & Analysis  
9/20/2005   Post a comment
Mentor Graphics Corp. named Arun Arora vice president and corporate treasurer.
Legend Design releases multiprocessing simulation manager
News & Analysis  
9/20/2005   Post a comment
Legend Design Technology released the CharFlo-MonteCarlo! simulation manager for multiprocessing statistical circuit simulation, which is bundled with the company's MSIM application program interface (API). The bundled product enables designers to examine the impacts of statistical Spice models and enhance designs for yield, according to the company.
Vehicle wiring software saves design time
Design How-To  
9/20/2005   Post a comment
Package reduces design drawing time and improves electric system reliability, manufacturability, and serviceability.
Xilinx introduces FPGA IP for controller area networks
Product News  
9/19/2005   Post a comment
Xilinx introduced what it said was the first field-programmable gate array intellectual property core for implementing controller area networks in automotive designs.
TI Fellow predicts 'third-wave' of DSP innovation
News & Analysis  
9/19/2005   Post a comment
A new wave of DSP-based innovation is just around the corner, according to Gene Frantz, a principal Fellow at Texas Instruments.
ESL design group float set to raise $18 million
News & Analysis  
9/19/2005   Post a comment
Electronic system level (ESL) design and synthesis vendor Celoxica plc is planning to float on the London Alternative Investment Market and expects to raise £10 million ($18 million), valuing the company at about £25 million ($45 million).
Synopsys aims JupiterIO at flip chip floorplanning
News & Analysis  
9/19/2005   Post a comment
Synopsys introduced JupiterIO, a new technology for enabling concurrent die and package floorplanning in flip chip design flows.
The history and future of scan design
News & Analysis  
9/19/2005   Post a comment
Scan design has thus far maintained a low profile, but nanometer design challenges and improved methodologies may herald a new era for scan, say authors from Synopsys.
Analysts give thumbs up to CDNLive!
News & Analysis  
9/16/2005   Post a comment
The announcements were not necessarily news, but EDA analysts expressed support for the new marketing tactics and technologies rolled out this week at Cadence Design Systems' user conference.
Madhavan stresses need for automation
News & Analysis  
9/15/2005   Post a comment
The term "EDA" is coming to stand for "electronic design assistance," according to Magma Design Automation Inc.'s Rajeev Madhavan, who warned that design tool vendors must provide more automation in order to extract greater value from customers.
Chris Mack joins tech advisory board of DFM startup
News & Analysis  
9/14/2005   Post a comment
Design-for-manufacturing provider Aprio Technologies announced added two members, including former KLA-Tencor executive Chris Mack, to its advisory board.
Court dismisses class action suit against Synopsys
News & Analysis  
9/14/2005   Post a comment
A class action lawsuit against Synopsys Inc. for alleged securities laws violations has been dismissed by the U.S. District Court for the Northern District of California.
AGEIA Tech chooses nSys verification suite
News & Analysis  
9/14/2005   Post a comment
Verification IP and services provider nSys Inc. said the nSys Verification Suite (nVS) for PCI Express verification has been selected by semiconductor IP company AGEIA Technologies Inc.
Si2 forms Open Modeling Coalition
News & Analysis  
9/14/2005   Post a comment
Si2 Wednesday launched a new coalition, modeling after the OpenAccess Coalition, to address critical issues in the characterization and modeling of libraries and intellectual property.
ESL Design methodology targets convergent DSP and FPGA
News & Analysis  
9/13/2005   Post a comment
Celoxica and Sundance are teaming with Xilinx Inc. on a customized electronic system design solution that they hope will bridge the gap between conventional design flows for DSP and FPGA systems.
Fister 'passionate' about kits
News & Analysis  
9/13/2005   Post a comment
Cadence Design Systems President and CEO Michael Fister kicked off the CDNLive! designer network conference Monday by extolling the virtues of the company's new methodology kits.
Accton offering single-chip, 48-port Ethernet switch
Product News  
9/13/2005   Post a comment
Taiwan's Accton Technology Corp. Tuesday has introduced a 48-port gigabit managed Ethernet switch powered by a single chip from Agere Systems.
Xilinx releases PowerPC, MicroBlaze development kit
News & Analysis  
9/12/2005   Post a comment
Xilinx released the PowerPC and MicroBlaze Development Kit, Virtex-4 FX12 Edition, touted as a comprehensive design environment with everything embedded developers need to create processor-based systems.
English companies form partnership around ESL
News & Analysis  
9/12/2005   Post a comment
Celoxica and Sundance will jointly offer out-of-the-box system design solutions backed up by partnerships with Texas Instruments Inc. and Xilinx Inc., the companies said.
Indian researchers propose new SoC test method
News & Analysis  
9/12/2005   Post a comment
With efficient test access architecture of much interest to the SoC design and test community, two researchers at an Indian technical institute have proposed a design-for-test method for digital SoC designs using a Test Access Mechanism (TAM) switch.
Multiprocessing speeds IC physical verification
News & Analysis  
9/12/2005   Post a comment
Authors from Cadence Design Systems discuss limitations of current IC physical verification approaches, and show how partitioning, multiprocessing and dedicated engines can speed the process.
Cadence speeds IC physical verification
Product News  
9/12/2005   Post a comment
Promising a "massively parallel" approach to IC design rule checking and layout-versus-schematic, Cadence Design Systems is rolling out its Physical Verification System for designs at 90 nm and below.
Analog/RF EDA startup joins Cadence Connections program
News & Analysis  
9/8/2005   Post a comment
Berkeley Design Automation has joined Cadence Design Systems' Connections program and integrated its PLL Noise Analyzer noise analysis tool with Cadence's Virtuoso analog design environment.
Cadence supporting OpenAccess 2.2
News & Analysis  
9/8/2005   Post a comment
Cadence Design Systems announced support of OpenAccess 2.2 as a unified database for its IC implementation platforms and design-for-manufacturing solutions.
Page 1 / 2   >   >>


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