Pyxis Announces NexusRoute
Product News 9/26/2007 Post a comment
Pyxis Technology has announced NexusRoute, a DFM-aware, yield-driven auto router that comprehends and optimizes manufacturability and yield concurrently with the actual routing and timing closure process.
FPGAs look for a lingua franca
Signal Processing DesignLine Blog 9/26/2007 Post a comment
ESL tools have made FPGA design a lot easier, but the lack of a common design language means the learning curve is still too steep.
Not your father's circuits
Blog 9/19/2007 Post a comment
The presenters at CICC are pointing out that some ofthe problems found at very-deep-submicron processes can be solved at the architectural level.
The Wireless Revolution Continues
Design How-To 9/18/2007 Post a comment
The majority of papers presented at this year's Custom Integrated Circuits Conference (CICC) deal with issues encountered in the design, development, and manufacturing of analog circuits for wireless applications. The keynote address, delivered by Dr. Bill Krenik, Chief Technical Officer for Texas Instruments' Wireless Terminals Business Unit, addressed issues in this segment of the market.
A New Approach to In-System Silicon Validation and Debug
Design How-To 9/16/2007 Post a comment
This is the first in a series of three articles about in-system at-speed silicon validation. It describes the silicon validation problem and the basic requirements of an effective and scalable solution. Part 2 will introduce a new approach that meets these requirements, and will describe basic applications. Part 3 will present the silicon results of four devices implemented with this solution.
ARM rolls Cortex-M1 kit for Cyclone III FPGAs
Product News 9/13/2007 Post a comment
ARM's new Cortex-M1 Development Kit is optimized for Altera's Cyclone III FPGAs. It has been integrated into Altera's Quartus II design software, and the core is configurable as a component in Altera's SOPC Builder tool.
Gary Smith to receive ACM Award
News & Analysis 9/12/2007 Post a comment
Gary Smith has been selected as recipient of a 2007 Computing Machinery/Special Interest Group on Design Automation (ACM/SIGDA) Distinguished Service Awards
Marketing to Customers: the Growth of Users Groups
Blog 9/11/2007 Post a comment
If you take the list of the top two hundred electronics companies in the world you have the EDA RAM (Relevant Available Market). Companies not on the list are not, with very few exceptions, going to provide a significant revenue stream worth the focused attention of the big four EDA vendors, who collectively control about 80% of the total industry's revenue.
Process Intelligent Modeling and Statistical STA improve DFM
Design How-To 9/11/2007 Post a comment
New technologies such as Statistical Static Timing Analysis (SSTA) are helping by taking much of the sting out of the variation crisis that designers are facing. The challenge now becomes enabling SSTA with a robust process-intelligent modeling methodology that can translate manufacturing data into usable statistical device, cell and interconnect models with requisite dependability.
Cadence Provides "WYDIWYG" Capability, Collaborates with Stratosphere Solutions
Product News 9/10/2007 Post a comment
Cadence Design Systems, Inc. announced a set of new design products and capabilities for faster production of digital system-on-chip (SoC) designs. According to Mike McAweeney, vice president of DFM marketing at Cadence, these new capabilities provide "what you design is what you get" (WYDIWYG) modeling and optimization for critical manufacturing variations during the design phase.
Top-down DSP design for FPGAs
Design How-To 9/5/2007 1 comment
High-level C++ synthesis in combination with FPGAs is an attractive solution for achieving a rapid path from C++ to RTL running in hardware.
Vivace launches VSP100 design tools
Product News 9/4/2007 Post a comment
Vivace Semiconductor has announced the availability of its VSP100 development and integration systems for the high-performance VSP100 media processing chip, aimed at consumer mobile applications.
DAC: An Independent Technical Program Committee
Blog 9/4/2007 Post a comment
In my blog of August 24, entitled "Vendors not the sole cause of declining DAC attendance", I may have given the impression that two of the three DAC sponsors, namely ACM and the IEEE have direct control over the contents of the Technical Program. I did not mean to imply this.
Introduction to and Regression Test for OCP SystemC Channel Models
Design How-To 9/4/2007 Post a comment
The Open Core Protocol"International Partnership Consortium has defined a high-performance and bus-independent interface protocol between IPs, usually referred to as the OCP Protocol, which provides a standard for a system designer such that the design time of the core interface can be greatly reduced and possible interface errors can be discovered at the early design stage.