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Content tagged with Design Tools (EDA)
posted in September 2010
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MathWorks upgrades system design tool
Product News  
9/15/2010   Post a comment
MathWorks has announced major new capabilities for MATLAB and Simulink, claiming that the SimRF product lets system architects use Simulink to design and verify complete wireless communication systems with true-to-form RF subsystem models and advanced circuit-envelope and harmonic-balance methods.
How do mirrors work (Part 2)
9/14/2010   9 comments
When you look in a mirror – it appears to invert your image Left-to-Right; Why not Top-to-Bottom?"
How to achieve 1 trillion floating-point operations-per-second in an FPGA
Design How-To  
9/14/2010   4 comments
Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs.
Hardware-in-the-loop (HIL) for FPGA Verification
9/14/2010   1 comment
One of the things I think is really rather clever is the cunning Hardware-in-the-loop (HIL) FPGA verification and debug solution from GateRocket in the form of their RocketDrive (hardware) and RocketVision (Software).
EDA modeling tool vendor names new CEO
News & Analysis  
9/14/2010   1 comment
Sam Young, a 35-year veteran of the semiconductor industry, was named president and CEO of privately held EDA firm Lynguent.
Sonics MemMax Amp memory scheduler
Product News  
9/13/2010   1 comment
IP vendor Sonics Inc. introduces MemMax AMP, a stand-alone memory scheduler in a single ip block.
Actel FPGAs with cryptographic cores offer DPA resistance
Product News  
9/13/2010   2 comments
Actel just announced that several of its FPGAs are now usable with cryptographic cores offering differential power analysis (DPA) resistance.
Actel launches direct sales channel in North America
News & Analysis  
9/13/2010   2 comments
Actel has just announced Actel Direct, a sales channel supplying North American customers with simple and streamlined direct sales, fulfillment, and application support.
QuickLogic introduces VEE Apps Builder for Android
Product News  
9/13/2010   1 comment
QuickLogic’s customizable VEE Apps Builder Android application facilitates mobile product differentiation by offering a better viewing experience and longer battery life.
Dolphin Integration's dual voltage panoply cuts power consumption by 7
Product News  
9/13/2010   Post a comment
EDA and IP company Dolphin Integration SA now tackles the dynamic power consumption challenge at the architectural level with the introduction of a panoply of memories and standard cells that offer dual voltage capability for the 180nm process.
MathWorks MATLAB and Simulink Enhancements: SimRF, System Objects, HDL Coder
Product News  
9/13/2010   4 comments
Launching new capabilities for RF modeling, streaming applications, and FPGA design flow, MathWorks supports algorithm-intensive wireless and multimedia system designs.
Xilinx demos real-time H.264/AVC-I compression
Product News  
9/10/2010   Post a comment
Xilinx and Vanguard Software Solutions have just demonstrated the ability to deliver a very low latency, ITU and Panasonic AVC-Intra compliant FPGA implementation of the industry-standard codec real-time video broadcast applications.
Xilinx FPGA development platform for 3D TV
Product News  
9/10/2010   Post a comment
Xilinx has just announced a new development platform for engineers working to meet the rapidly growing demand for 3D TV broadcast and other high definition video applications.
Audio FPGAs Codecs from Xilinx and Coreworks
Product News  
9/10/2010   1 comment
Xilinx and Coreworks have just announced the availability of a range of new Dolby and other audio codec IP cores for compressing multichannel audio in FPGAs.
Best book for FPGA newbies?
9/10/2010   9 comments
I know this is a moving target because new books are always leaping onto the scene, but any recommendations you have would be very much appreciated...
Design convergences: approaches on handling the coming tsunami
9/10/2010   Post a comment
It is true that designs are going to have to meet the following requirements: increasing levels of integration of analog and digital components on the same silicon substrate, lower power consumption targets (both standby and operational) and higher performance requirements. It is also true that these have to be done within compressed design schedules and with smaller design teams spread out all over the world.
Amazingly funny videos
9/9/2010   1 comment
You are going to hate me for this, but I just ran across a really great website that contains some very, very funny videos. It's not my fault if you don’t have the willpower to resist... don’t shoot the messenger...
Engineer's video blogs are funny and interesting
9/9/2010   5 comments
Presented in a uniquely enthusiastic style, these unscripted video blogs by an Australian engineer manage to be both funny and interesting at the same time.
Tanner EDA rolls Linux version of analog IC design suite
Product News  
9/8/2010   Post a comment
Tanner EDA announced it has delivered HiPer Silicon v15.02, a Linux version of its HiPer Silicon full-flow design suite, so that customers can choose –and change as desired- between the Windows and the Linux platforms.
How to build a Magic Mirror (Part 1)
Design How-To  
9/8/2010   11 comments
Just a few days ago as I pen these words, I came across about a very cool website that describes a really cunning idea called a Magic Mirror, so I decided to build one...
Are FPGA tools dumb?
9/7/2010   4 comments
In a recent discussion about the necessary differences between tools for ASIC developers as compared to the needs of FPGA users, one expert called it 'a dumbing down,' but guest blogger Brian Bailey says 'that is just wrong.'
Why modelling is the most advanced in telecommunication
Design How-To  
9/7/2010   Post a comment
This article focuses on the usage of modeling technologies in the telecommunication domain in order to demonstrate how advanced it is compared to other domains.
Toshiba uses Catapult C for complex ASIC designs
Product News  
9/7/2010   Post a comment
Toshiba Information Systems Corp. said it has expanded the deployment of Mentor Graphics Corp.'s Catapult C tool for the high-level synthesis of next generation ASICs for audio, communications and image processing systems.
Do we need an international EDA roadmap?
Design How-To  
9/7/2010   1 comment
When asked if the EDA industry has a roadmap, Joseph Borel, ex-executive vice president in central R&D at STMicroelectronics NV (Switzerland, Geneva), answers affirmatively as Europe continually renews the Medea+ EDA roadmap. The real question should however be: Does the EDA industry need an international roadmap?
Xbox team uses SpringSoft's Verdi debug tool
Product News  
9/7/2010   Post a comment
Microsoft Corp.'s Xbox development team said it has licensed SpringSoft's Verdi Automated Debug System to slash design time and manage new levels of complexity in the latest generation of chips.
AWR readies visual system simulator 2010
Product News  
9/6/2010   Post a comment
EDA vendor AWR Corp. said the 2010 Visual System Simulator (VSS) software suitable for the design of today's complex communications systems is now commercially available.
C-to-FPGA integration gives prototyping 10X boost!
News & Analysis  
9/3/2010   7 comments
New integration enables software developers to write HLL (high level language) algorithms that rapidly compile to optimized RTL (run time language) on FPGA board and development kit.
Reproducing a Cray 1 supercomputer in a single FPGA
Design How-To  
9/3/2010   6 comments
Now here's something you don’t see every day – a reproduction of a Cray 1 supercomputer using a single FPGA on a Xilinx Spartan-3E 1600 development board.
How to train your boss in the proper bug etiquette
Engineering Pop Culture!  
9/3/2010   8 comments
An engineer gets back at a boss butting in.
DAC attendees reinforce need for industry events
9/3/2010   3 comments
If exhibitors are looking ahead to DAC 2011, they are likely wondering how to connect better with designers and understand how they can better help them. At Magma, we decided the best approach was to ask them, and what we learned in our post-DAC survey of attendees will (we hope) serve as a useful guide to planning. We’ll share what we learned –– well, some of what we learned.
Unpack, switch on and get going
Product How-To  
9/3/2010   6 comments
Great computing power, a high level of integration and energy efficiency are just some of the demands made of the latest electronics for embedded designs. Impressive graphics quality is also required, primarily in the price-sensitive industrial and automotive market segments. A starter kit for a special graphics controller is now set to provide a simple introduction to the world of graphics.
New techniques for PDN modeling promise more accurate power noise predictions
9/3/2010   3 comments
The bad news is that power distribution noise requirements will be getting more difficult to meet, but the really bad news is that the actual on-die power noise you currently have is probably much larger than you think.
Startup offers 'variability' modeling service
News & Analysis  
9/2/2010   4 comments
Gold Standard Simulations Ltd., a spin-off from the University of Glasgow, offers to help chip designers model how circuits made from variable nanometer-scale transistors will perform.
Russian SoC designers take Virage IP for TV
News & Analysis  
9/1/2010   2 comments
Semiconductor circuit licensor Virage Logic Corp. has announced that Microelectronics Research Institute Progress has licensed the ARC Video 401V subsystem.
GlobalFoundries shows 28-nm AMS design kit
Product News  
9/1/2010   1 comment
GlobalFoundries is making a 28-nm analog/mixed-signal design flow development kit available to customers, the company said at the opening of its Global Technology Conference in Santa Clara, California.
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