Yes, it is art!
Engineering Pop Culture! 9/26/2012 5 comments
These ceramic versions of tin cans were created by a mathematician called Ned who specializes in chaos theory.
EDA/IP Weekly Roundup – September 26th
Blog 9/26/2012 Post a comment
Dongbu HiTek, EMA, Symtavision, Synopsys, Globalfoundries, element14, Cadence, Analog Devices, ProPlus, ChipEstimate, Aldec, CEDA, X-Fab and more made the lineup today. See here for their news…
Cadence announces Allegro 16.6
Product News 9/25/2012 Post a comment
Allegro packs a bunch of new capabilities into this new release hoping to accelerate timing closure for high-speed interfaces through timing-aware physical implementation and verification within an ECAD team collaboration environment...
LVS Debug: The Good, The Bad, and The Future
Blog 9/25/2012 Post a comment
LVS debug of today's complex designs is challenging and time-consuming, but reducing LVS debug time while continuing to provide reliable, high-performance designs is a requirement for chip designers who want to meet their tight tapeout deadlines and satisfy customers.
ARM TechCon explores road to 14-nm ICs
News & Analysis 9/17/2012 10 comments
A tutorial presentation at the upcoming ARM TechCon exhibition and conference is set to discuss the mix of challenge and opportunity represented by the 14-nm manufacturing node which lies two or three years away from mass production.
Understanding clock domain crossing issues
Design How-To 9/17/2012 3 comments
In today's complex system on chip (SoC) designs, multiple clocks have become the norm. Thus, clock domain crossings (CDCs) are an integral part of any SoC. The main problems which can occur in a clock domain crossing are metastability, data loss and data incoherency. In this paper, we discuss all these issues for different types of synchronous and asynchronous clock domain crossings.
EDA/IP Weekly Roundup – September 12th
Blog 9/12/2012 Post a comment
Xilinx, Altera, UMC, Breker, ASML, Aselta, ASSET, Oski, Carbon, X-fab, CEVA and Mentor the lineup today. See here for their news…
I want a Beard Beanie!
Programmable Logic DesignLine Blog 9/12/2012 9 comments
I know I'm being silly, but I just ran across something called a "Beard Beanie" that I think is really fun in a strange sort of way...
EDA Countdown: 4-6
Blog 9/11/2012 Post a comment
This is a countdown of the top ten design articles seen in the EDA Designline during my first year at the helm...
LCD dot matrix solutions with ultra-low-power MCUs
Design How-To 9/10/2012 4 comments
Using design techniques to optimize the system hardware and software, low-cost, ultra-low-power microcontrollers can be used to drive dot matrix LCD displays that previously required larger, power-hungry processors.
Driving Blindfolded – Solving The Triage Challenge
Design How-To 9/10/2012 Post a comment
When regression tests fail, an engineer must decide which failing tests should be further analyzed and by whom - a process called triage. The challenge is the dearth of information about the bug and its creator at this early stage...