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posted in September 2012
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The Oski 72 hour challenge
Blog  
9/27/2012   Post a comment
What was the Oski 72 hours DAC challenge all about and will they do it again next year?
Strategic investments, partnerships drive EDA innovation
Blog  
9/27/2012   Post a comment
With traditional sources of venture funding drying up, small EDA firms turn to the big companies that depend on their tools.
Rock-Paper-Scissors-Lizard-Spock
Engineering Pop Culture!  
9/27/2012   15 comments
Ha! 10 points to me I think!
Yes, it is art!
Engineering Pop Culture!  
9/26/2012   5 comments
These ceramic versions of tin cans were created by a mathematician called Ned who specializes in chaos theory.
Xilinx All Programmable FPGAs used in robotic-assisted surgical app
News & Analysis  
9/26/2012   Post a comment
Xilinx is recognized for the inventive use of All Programmable FPGAs for 3D vision and precise control in minimally-invasive da Vinci Surgical System.
Aldec-Altera free DO-254 Webinar
Product News  
9/26/2012   6 comments
Sign Up for This Free Webinar -- How to Increase Verification Coverage by Test
Aldec's Active-HDL helps manage complex FPGA projects
Product News  
9/26/2012   Post a comment
Active-HDL 9.2, an HDL-based FPGA Design and Simulation solution, allows engineers to effortlessly manage complex FPGA projects.
EDA/IP Weekly Roundup – September 26th
Blog  
9/26/2012   Post a comment
Dongbu HiTek, EMA, Symtavision, Synopsys, Globalfoundries, element14, Cadence, Analog Devices, ProPlus, ChipEstimate, Aldec, CEDA, X-Fab and more made the lineup today. See here for their news…
Cadence announces Allegro 16.6
Product News  
9/25/2012   Post a comment
Allegro packs a bunch of new capabilities into this new release hoping to accelerate timing closure for high-speed interfaces through timing-aware physical implementation and verification within an ECAD team collaboration environment...
LVS Debug: The Good, The Bad, and The Future
Blog  
9/25/2012   Post a comment
LVS debug of today's complex designs is challenging and time-consuming, but reducing LVS debug time while continuing to provide reliable, high-performance designs is a requirement for chip designers who want to meet their tight tapeout deadlines and satisfy customers.
Texas Instruments unveils mega-cool Stellaris LaunchPad
Product News  
9/25/2012   Post a comment
Engineers of all experience levels can now explore Stellaris ARM Cortex-M4F microcontrollers with an easy-to-use kit priced at less than $5 USD!
Book excerpt: Mixed-signal methodology guide part 3
Blog  
9/25/2012   Post a comment
This book, Mixed-signal Methodology Guide provides a broad overview of mixed-signal design, verification and implementation methodologies…
Book excerpt: High-level synthesis blue book - part4
Blog  
9/25/2012   Post a comment
The promise of high-level synthesis (HLS) is a powerful one: the ability to generate production-quality register transfer level (RTL) implementations from high-level specification...
New Atmel Cortex-M4 MCUs consume 66% less power…
Product News  
9/24/2012   2 comments
Devices run 90uA/MHz in active mode, deliver 28 CoreMark/mA, and consume 1.5uA in sleep mode with full RAM retention and 1.5us wake-up time.
STMicro's Smart-card MCUs increase security and flexibility
Product News  
9/24/2012   Post a comment
First secure microcontrollers to feature auto contactless-reader detection add secure hardware cryptography plus flexible memory and interface options.
Vote for DCD’s DQ80251 – the world’s fastest 8051 CPU
Blog  
9/24/2012   3 comments
Digital Core Design has been nominated as the only IP Core and SoC design house for the European Business Award, and they are asking their friends for support…
OEMs and semiconductor suppliers take turns driving innovation and integration
Design How-To  
9/24/2012   Post a comment
The 20th century artifact of the serial EEPROM may finally give way to the 21st century antifuse NVM IP.
Book Review: Empower Your Inner Manager by Ian Mackintosh
Engineer’s Bookshelf  
9/21/2012   Post a comment
if you want to be a manager – or if you are already a manager – I would really appreciate it if you would read this book.
What were they thinking: do you know your Rapunzel Number?
Blog  
9/21/2012   11 comments
The Nobel prizes are awarded every year for significant contributions to science, literature and peace, but do you know about the Ig Nobel prizes?
Power2U – What a jolly good idea!
Programmable Logic DesignLine Blog  
9/20/2012   9 comments
In addition to two regular power sockets, this little beauty also has two USB ports capable of charging iPhones and iPads.
EDA/IP Weekly Roundup – September 19th
Blog  
9/19/2012   Post a comment
Cadence, Synopsys, EVE, Kilopass, Aldec, Digital Core Design, Sisvel, SMIC and IC Insights made the lineup today. See here for their news…
Book excerpt: Mixed-signal methodology guide part 2
Blog  
9/19/2012   Post a comment
This book, Mixed-signal Methodology Guide provides a broad overview of mixed-signal design, verification and implementation methodologies…
Collaborative Advantage: The Future of Fabless Design?
Blog  
9/18/2012   3 comments
Virtual reaggregation is necessary to re-aligning data dependencies that were split apart from disaggregation of the supply chain…
TI introduces new SafeTI MCUs and PSU for safety-critical apps
Product News  
9/18/2012   2 comments
Latest 32-bit Hercules RM4x safety MCUs, TPS65381-Q1 power supply, software and documentation help designers more easily achieve IEC 61508 SIL-3 safety standards.
New SafeTI functional safety design packages from Texas Instruments
Product News  
9/18/2012   2 comments
Customers can more easily achieve IEC 61508, IEC 60730 and ISO 26262 safety certification for industrial, transportation, automotive and medical applications.
Book excerpt: High-level synthesis blue book - part3
Blog  
9/18/2012   Post a comment
The promise of high-level synthesis (HLS) is a powerful one: the ability to generate production-quality register transfer level (RTL) implementations from high-level specification...
EDA Countdown: top three
Blog  
9/18/2012   Post a comment
This concludes a countdown of the top ten design articles seen in the EDA Designline during my first year at the helm...
Sensor-fusion MCU kit from STMicroelectronics
Product News  
9/17/2012   Post a comment
Easy-access development kit combines power of STM32 F3 DSP core and floating-point arithmetic with MEMS gyroscope and e-compass for sensor-fusion applications.
Microchip adds 15 new 8-bit PIC MCUs to USB portfolio
Product News  
9/17/2012   Post a comment
Three scalable, eXtreme low power families offer substantial system cost savings by eliminating external crystal; available with a wide range of features.
Xilinx acquires wireless backhaul solutions provider
Product News  
9/17/2012   Post a comment
Proven backhaul technology and design expertise accelerates time-to-market for wireless mobile backhaul platforms based on Xilinx All Programmable FPGAs.
Predictable semiconductor cycle ahead?
Blog  
9/17/2012   2 comments
Despite the increasingly negative predictions of semiconductor forecasters, predictable change in the semiconductor industry comes from monitoring capital investment.
Power domain verification: Beyond traditional DRC, LVS and ERC
Blog  
9/17/2012   Post a comment
For many power domain issues, functional simulation can be performed successfully without catching the circuit error...
ARM TechCon explores road to 14-nm ICs
News & Analysis  
9/17/2012   10 comments
A tutorial presentation at the upcoming ARM TechCon exhibition and conference is set to discuss the mix of challenge and opportunity represented by the 14-nm manufacturing node which lies two or three years away from mass production.
Understanding clock domain crossing issues
Design How-To  
9/17/2012   3 comments
In today's complex system on chip (SoC) designs, multiple clocks have become the norm. Thus, clock domain crossings (CDCs) are an integral part of any SoC. The main problems which can occur in a clock domain crossing are metastability, data loss and data incoherency. In this paper, we discuss all these issues for different types of synchronous and asynchronous clock domain crossings.
A package just arrived on my desk…
Programmable Logic DesignLine Blog  
9/14/2012   32 comments
What if I were to find myself an old Webster wire recorder and load this spool, would I hear an ethereal voice saying something like…
What were they thinking: The world is your lawyer
Blog  
9/13/2012   9 comments
Freescale makes a contest out of invalidating a patent. Do you want to be the next patent lawyer and find the technology that makes the point…
Microsemi, Emcraft deliver FPGA-based SOM for embedded apps
Product News  
9/12/2012   Post a comment
Miniaturized System-on-Module (SOM) features SmartFusion cSoC with ARM Cortex-M3 and uClinux.
Opal Kelly adds QNX RTOS support to its FrontPanel/USB SDK
Product News  
9/12/2012   Post a comment
Combined with Opal Kelly's FPGA modules, this little rascal can save 70% of development time/cost.
EDA/IP Weekly Roundup – September 12th
Blog  
9/12/2012   Post a comment
Xilinx, Altera, UMC, Breker, ASML, Aselta, ASSET, Oski, Carbon, X-fab, CEVA and Mentor the lineup today. See here for their news…
I want a Beard Beanie!
Programmable Logic DesignLine Blog  
9/12/2012   9 comments
I know I'm being silly, but I just ran across something called a "Beard Beanie" that I think is really fun in a strange sort of way...
CEO Spotlight: Ellis Smith, Blue Pearl Software
Blog  
9/12/2012   Post a comment
Ellis Smith, CEO of Blue Pearl talks about the approach they are taking for being successful in the FPGA software market…
Book excerpt: Mixed-signal methodology guide
Blog  
9/12/2012   2 comments
This book, Mixed-signal Methodology Guide provides a broad overview of mixed-signal design, verification and implementation methodologies…
Choosing your business strategy
Blog  
9/12/2012   Post a comment
Entrepreneur Maheen Hamid looks beyond the iconic opposites to offer advice on your business strategy.
Opinion: Why IDEs for hardware design fail
Blog  
9/11/2012   10 comments
Hardware designers hate integrated development environments (IDEs), and they have good reasons to do so...
EDA Countdown: 4-6
Blog  
9/11/2012   Post a comment
This is a countdown of the top ten design articles seen in the EDA Designline during my first year at the helm...
Book excerpt: High-level synthesis blue book - part2
Blog  
9/11/2012   Post a comment
The promise of high-level synthesis (HLS) is a powerful one: the ability to generate production-quality register transfer level (RTL) implementations from high-level specification...
LCD dot matrix solutions with ultra-low-power MCUs
Design How-To  
9/10/2012   4 comments
Using design techniques to optimize the system hardware and software, low-cost, ultra-low-power microcontrollers can be used to drive dot matrix LCD displays that previously required larger, power-hungry processors.
"Under the hood" of Altera's 20nm offerings
Programmable Logic DesignLine Blog  
9/10/2012   Post a comment
While chatting with Misha Burich, CTO at Altera, I learned myriad tidbits of trivia and nuggets of knowledge of which I was previously unaware…
Driving Blindfolded – Solving The Triage Challenge
Design How-To  
9/10/2012   Post a comment
When regression tests fail, an engineer must decide which failing tests should be further analyzed and by whom - a process called triage. The challenge is the dearth of information about the bug and its creator at this early stage...
London Calling: Sony set to make Raspberry Pi
Blog  
9/10/2012   16 comments
Sony will make low cost, credit card-sized single board computers called Raspberry Pi. Would something closer to the real world do more to excite young people's interest?
Page 1 / 2   >   >>


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