Jitter and timing analysis in the presence of crosstalk Design How-To 12/14/2011 3 comments Serial data standards continue to proliferate, providing dramatic improvements in PC and Server system performance. Testing these higher speed standards for evidence of jitter is critical for long-term stability and to achieving the objective of a good Bit Error Ratio (BER) in the design. Effective analysis begins with selecting the right instruments and have a good understanding of instrument noise, rise time and factors such 3rd, 4th, 5th harmonic performance.
Defining the 4G PHY architecture design challenges Design How-To 12/5/2011 2 comments As with most emerging technologies, design challenges for LTE-A abound, particularly when it comes to the physical layer (PHY) architecture development. Addressing these challenges remains critical to the successful development and deployment of LTE-A designs.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments