Jitter and timing analysis in the presence of crosstalk Design How-To 12/14/2011 3 comments Serial data standards continue to proliferate, providing dramatic improvements in PC and Server system performance. Testing these higher speed standards for evidence of jitter is critical for long-term stability and to achieving the objective of a good Bit Error Ratio (BER) in the design. Effective analysis begins with selecting the right instruments and have a good understanding of instrument noise, rise time and factors such 3rd, 4th, 5th harmonic performance.
Defining the 4G PHY architecture design challenges Design How-To 12/5/2011 2 comments As with most emerging technologies, design challenges for LTE-A abound, particularly when it comes to the physical layer (PHY) architecture development. Addressing these challenges remains critical to the successful development and deployment of LTE-A designs.
Battle-hardened veterans of the electronics industry have heard of the “connected car” so often that they assume it’s a done deal. But do we really know what it takes to get a car connected and what its future entails? Join EE Times editor Junko Yoshida as she moderates a panel of movers and shakers in the connected car business. Executives from Cisco, Siemens and NXP will share ideas, plans and hopes for connected cars and their future. After the first 30 minutes of the radio show, our listeners will have the opportunity to ask questions via live online chat.