Jitter and timing analysis in the presence of crosstalk Design How-To 12/14/2011 3 comments Serial data standards continue to proliferate, providing dramatic improvements in PC and Server system performance. Testing these higher speed standards for evidence of jitter is critical for long-term stability and to achieving the objective of a good Bit Error Ratio (BER) in the design. Effective analysis begins with selecting the right instruments and have a good understanding of instrument noise, rise time and factors such 3rd, 4th, 5th harmonic performance.
Defining the 4G PHY architecture design challenges Design How-To 12/5/2011 2 comments As with most emerging technologies, design challenges for LTE-A abound, particularly when it comes to the physical layer (PHY) architecture development. Addressing these challenges remains critical to the successful development and deployment of LTE-A designs.
In conjunction with unveiling of EE Times’ Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. One of Silicon Valley's great contributions to the world has been the demonstration of how the application of entrepreneurship and venture capital to electronics and semiconductor hardware can create wealth with developments in semiconductors, displays, design automation, MEMS and across the breadth of hardware developments. But in recent years concerns have been raised that traditional venture capital has turned its back on hardware-related startups in favor of software and Internet applications and services. Panelists from incubators join Peter Clarke in debate.