Circuit lets you test sample-and-hold amplifiers - measure voltage drop with a digital voltmeter Design How-To 6/29/2011 1 comment Sample-and-hold amplifiers sample an analog voltage and hold it until an ADC can digitize it. A perfect sampling circuit holds a voltage until digitizing is complete. Thus, the amplifier’s output is identical to its input. Real sample-and-hold amplifiers, however, can gain or lose voltage, producing an error. Offset voltages in amplifiers cause a static additive error. Further, there occurs a specific additive error, the so-called voltage pedestal, which originates within the transition from th
Hybrid test bed for real-time communication systems Design How-To 6/22/2011 Post a comment This paper describes an FPGA and Matlab-based hybrid solution dedicated for real-time communication tests. The main idea is to use an FPGA-based RT Ethernet device for simulation of communication errors. The next issue is Matlab-based software architecture for monitoring communication disturbances.
ECU architecture ensures failure safety Design How-To 6/17/2011 3 comments The complexity of automotive mechatronic systems makes it impossible to fully determine all potential failure modes or to test all possible behavior. The challenge is to architect control units in a way that dangerous failures are prevented or at least sufficiently controlled.
Oscilloscopes and ENOB Design How-To 6/15/2011 12 comments For scopes with bandwidth in the GHz range, one quality metric involves characterizing a scope’s analog-to-digital converter (ADC) using effective number of bits (ENOB). In a new design article added this week Joel Woodward and Brig Asay of Agilent Technologies explain that when selecting which scope to use, how important ENOB is and how effective ENOB is at predicting a scope’s measurement accuracy.
'Bit-Reshaper' corrects FlexRay timing errors Design How-To 6/10/2011 1 comment EMI susceptibility and signal quality issues with complex topologies have prevented a breakthrough of the FlexRay automotive data bus. But here's how to correct bit timing mismatches and significantly improve overall signal quality in FlexRay networks.
IJTAG standard holds promise for 3D chip test Design How-To 6/8/2011 1 comment IEEE P1687 Internal JTAG (IJTAG) standardizes the interface to validation and test instruments that are embedded in individual 3D chip dies, simplifying their use and deployment, and hastening the development of a marketplace for third-party tools and other related intellectual property.
Kozio adds support for Freescale's QorIQ P2 Product News 6/6/2011 Post a comment Kozio Inc. has expanded its in-system diagnostics solution to support Freescale Semiconductor's QorIQ P2 Platform Series, which includes the P2020 (dual-core) and P2010 (single-core) communications processors.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments