Managing signal integrity in tomorrow's high-speed flash-memory-system designs Design How-To 7/19/2011 Post a comment Next-generation flash-memory technology will tout data-transfer rates as much as 10 times faster than currently available. However, increasing distortions in the data-carrying digital signals can cause data-transfer failures, complicating the management of signal integrity. Proper design strategies can help you deliver reliable, high-performance products.
Freedom of choice in platforms Blog 7/19/2011 Post a comment This year has seen three test platforms continuing to develop their market message and attract new users from older platforms such as GPIB and VXI, the choices seem to continue to expand for users.
Minimizing cable-induced measurement errors in high current applications Blog 7/13/2011 Post a comment In my job as an applications engineer, I’ve been fielding lots of calls about test and measurement problems that engineers encounter with high current applications like characterizing high power LED modules and high brightness light-emitting diodes (HBLEDs). At higher test currents, the appropriate cabling techniques are particularly important in obtaining repeatable and accurate measurements and maximizing performance.
Is your probing setup good enough to measure DDR3 signal integrity? Design How-To 7/13/2011 5 comments DDD3 memory interface speeds have been going up steadily and are now approaching 2000 Mbps data rates. DDR4 is also nearly round the corner . At these high data rates, it is becoming increasingly difficult to get good probing solutions which allow performing Signal Integrity characterization. High speed characterization is considered important for silicon based product development cycle. It is needed to understand the limitations of the current generation of DDR interface designs and to gear
Advantest announces NAND flash test solutions Product News 7/11/2011 Post a comment Advantest Corporation announced the availability of two new solutions for next-generation NAND flash memory test: the T5773 for package test and the HA5100CELL, based on the Harmonic architecture, for wafer test.
Understanding the impact of digitizer noise on oscilloscope measurements Design How-To 7/6/2011 1 comment Whether you are designing or buying a digitizing system, you need some means of determining real-life performance. How closely does the output of any ADC, waveform digitizer, or DSO follow an analog input signal? ENOB testing provides a means of establishing a figure of merit for dynamic digitizing performance.
Tektronix buys validation tool vendor News & Analysis 7/5/2011 3 comments Test and measurement vendor Tektronix announced the acquisition of ASIC/FPGA prototyping debug software provider Veridae Systems. Terms of the acquisition were not disclosed.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments