The panelists had all been participants last March in a National Science Foundation-sponsored workshop that considered the challenges of billion-transistor systems. That workshop produced a document outlining recommendations in such areas as intellectual property, architectures, interconnect and verification.

Perhaps the most provocative statement at the ICCAD panel was made by Randy Harr, director of research at Synopsys Inc. (Mountain View, Calif.). "I don't think we'll need hardware designers," he said. "By 2010 we're going to have three chip companies and 10 designs, and instead of doing hardware design, everybody is going to be writing firmware and software." Harr emphasized that he wasn't speaking for Synopsys.

Other panelists agreed that the future will bring more programmable chips and much more embedded software development, but they weren't ready to take things quite so far. "I think we'll gravitate to a few microcontroller and DSP architectures, but numerous chips handling many functions," said Wayne Wolf, professor of electrical engineering at Princeton University.

Harr called for better technology in such areas as requirements capture, system description, hardware/software codesign and algorithm development. In response to a question from the audience, he said that billion-transistor chips will not be designed using HDLs. He suggested that functional programming languages can be applied to chip design.

Jason Cong, professor of computer science at the University of California at Los Angeles, called for a transition from today's device-oriented approach to an "interconnect-centric" design methodology. "Global interconnect is going to dominate everything as technology scales," he said.

Cong called for three kinds of tools: interconnect planning, interconnect synthesis and interconnect layout. He said that planning tools should work at the architectural, register-transfer and physical levels. At the architectural level, for instance, designers would consider the number of layers, the metal and isolation materials used for each layer and the thickness of various layers.

RTL planning would allow for a definition of global and local interconnect and for estimates that can guide synthesis. Physical planning would look at such concerns as delays under different pitch spacing.

Interconnect synthesis, as defined by Cong, would include delay, skew and signal-integrity optimization. For layout, he said, what's needed is a multilayer area router that is "gridless, flexible and efficient."

Ken Shepard, assistant professor of electrical engineering at Columbia University, noted that interconnect is not the only concern with billion-transistor chips. He talked about such concerns as simultaneous switching, charge-sharing, a decreasing signal-to-noise ratio, increased power consumption and the mixing of analog and RF devices on chip.

All this adds up to a "much more complex electrical environment," said Shepard. Interconnect will look increasingly like transmission lines, and it will be harder to communicate across the chip. "It will be increasingly difficult to distribute a low-skew clock," he said. "You're not going to be able to have a single global clock across the chip any more."

What's needed, Shepard said, are better static-estimation and analysis tools, along with the use of hierarchy to manage complexity.

Wolf stressed the importance of early analysis with architectural and codesign tools. "Errors must be discovered early, so you avoid designing the wrong billion-transistor chip," he said.

Wolf called for architectural-exploration tools that provide synthesis and offer performance and power estimation; component-design tools that include simulation and performance and power analysis; and system-integration tools that include simulation and formal methods.

One question that the audience asked more than once was what applications will require billion-transistor chips. Panelists generally agreed that these chips will predominantly consist of memory. A billion-transistor chip would allow an MPEG decoder with a 1,000-frame memory on-chip, Wolf noted.

"History teaches us that no matter how many transistors we have, people find ways to use them," he said.