The integration of synthesis and layout has become a major issue in EDA because designers are having difficulty meeting timing closure, and are having to iterate multiple times between logical and physical design. But the question of how this integration should be achieved has become ensnared in EDA vendor politics.

Synopsys Inc. (Mountain View, Calif.) argues that the correct approach is to start with synthesis, then and add placement and global routing. Cadence Design Systems Inc. (San Jose, Calif.) and Avant! Corp. (Fremont, Calif.), on the other hand, propose to add synthesis features to their layout tools. And newcomers such as Sapphire Design Automation (Santa Clara, Calif.) and Silicon Perspective Corp. are proposing third-party placement and optimization tools that sit between synthesis and routing.

All of these points of view were heard at the ISPD panel on layout and synthesis — as well as the controversial argument advanced by Kurt Keutzer, professor of electrical engineering and computer science at the University of California at Berkeley, that merging synthesis with layout is not necessary if blocks are kept under 50,000 gates. Keutzer argued that with new materials and proper drive strengths, interconnect delays will actually decrease at this level.

Raul Camposano, chief technology officer of Synopsys, said that "push-button" synthesis and layout tools are on the near horizon for blocks up to one million gates. Synthesis-driven layout, he argued, allows for much higher-level optimizations than adding more capabilities to placement and routing — or than the "worse idea" of putting a third-party tool between synthesis and routing.

Lou Scheffer, fellow at Cadence, said that synthesis-driven layout is most useful for chip designs that are not aggressive. For harder problems, he said, layout-driven synthesis automates difficult top-level decisions and reaches more of the solution space.

Michael Jackson, head of product marketing at Avant!, said both approaches are needed. He described Avant!'s Planet-RTL floor planner as an example of layout-driven synthesis, and Avant!'s Saturn placement and optimization tool as an example of synthesis-driven layout. He also emphasized the importance of a deep-submicron database.

Jackson said that a Sapphire type of solution will result in "unnecessary handoffs" and sever the tight link that's needed between global and detailed routing. Sheffer said that the Sapphire approach falls short because it assumes synthesis tools will still use wire-load models, which are not a good starting point.

Hit from all sides, Shashank Goel, president and chief executive officer of Sapphire Design Automation, said his company is offering real innovation by bringing an "electrical design view" to placement and optimization. The big EDA vendors, he said, are just integrating existing capabilities.

"The issue is not that it's an additional step," Goel said. "The issue is that between synthesis and routing is the right place to do these things."

Although his company has yet to formally announce a product, Lukas Van Ginneken, principal engineer at Magma Design Automation (Palo Alto, Calif.), threw down the gauntlet on the side of layout-driven synthesis. His company still envisions a two-part flow separating logical and physical design, but with synthesis-like features added to placement and routing, such as "layout-driven" buffer sizing.

But from Keutzer's point of view, all of these vendors are going in the wrong direction. "The real problem is not the integration of synthesis and placement," he said. "What will grind us to a halt is the chip-level assembly issues."

At ISPD, Keutzer and Dennis Sylvester, a UC Berkeley graduate student, presented a paper that outlined a global wiring approach for chips with large numbers of 50,000-gate blocks. Under fire at the panel session, Keutzer argued that the chip assembly problem can be made manageable with soft cores, hierarchical design, and the use of register bounding on the blocks.

Jason Cong, professor of computer science at the University of California at Los Angeles, also argued that the merging of synthesis and layout misses the point. He advocated an "interconnect-centric" design flow starting with "interconnect planning," which will help designers determine routing layers, materials and wire widths. The next step is "interconnect synthesis," which can perform buffer insertion, wire sizing and shaping, and simultaneous device and interconnect optimization.

Majid Sarrafzadeh, professor of electrical and computer engineering at Northwestern University, said that layout-aware synthesis will provide better "predictors" of circuit behavior, while synthesis-aware placement will help achieve timing closure.

There were no designers on the panel, but Chris Malachowsky, director of engineering at Nvidia Corp. (Santa Clara, Calif.), had already put in his vote for "yes to both" during his earlier keynote address. "I want synthesis to be layout-aware so I can make the right architectural trade offs, and I want layout to do whatever level of fix-up, clean-up or re-optimization is necessary to give the best results," he said.