Monterey, Calif. — Power and signal-integrity problems are approaching critical mass and will soon force changes in the nanometer IC design flow. But CAD methodology experts speaking here last week said that the industry is on the case.

Presenters at the Electronic Design Processes 2004 workshop discussed developments in behavioral-level power analysis, "policy-based" power management and dynamic power extensions to Verilog. They also investigated the power problems posed by FPGAs and microprocessors.

"Signal integrity and power are becoming such a crisis for the industry that they're not only affecting algorithms; they're also changing the flow itself," said Juan-Antonio Carballo, staff member at IBM Research and chairman of EDP-2004.

"The future is going to be very noisy," Li-Pen Yuan, R&D director for extraction and signal integrity at Synopsys Inc., said in a keynote speech. Yuan showed how crosstalk and power analysis change assumptions made throughout the design flow. "The problem involves the entire chip and system. To solve the problem in a divide-and-conquer way is going to be very complicated."

Yuan acknowledged that some problems can be solved with incremental changes to existing design systems. Those include hot-current effects and signal electromigration. Others, like timing, can be solved by making more information available.

But some, such as power in multi-Vdd or multimode designs, change the fundamentals of existing software systems. And crosstalk and resistive shielding challenge the fundamentals of the design flow.

Crosstalk, Yuan said, introduces spatial correlations between signals. "Before, you only had logical correlations, but now you have to look at the physical proximity of routing." Solving the problem requires that routing patterns, drive strength, clock domains and timing windows be taken into account, which can drive up complexity exponentially, he said.

Crosstalk analysis must also consider the nonlinear behavior of digital circuits, requires models with more attributes, demands additional physical and timing constraints, and calls for a reduction of pessimism, Yuan said. And "crosstalk destroys hierarchy. A lot of assumptions made in the hierarchical flow must be revisited."

No single step or tool by itself can solve crosstalk, Yuan said. A crosstalk-aware design flow must include placement, global routing and engineering change orders. Aggressiveness in prevention and correction must be balanced with timing, power and area concerns.

Power analysis, Yuan noted, is complicated by power-management techniques, which are aimed at reducing dynamic and leakage power. Such techniques may include multiple voltages, clock gating and "modes" that shut down portions of the chip to conserve power. There's a real need for multimode power analysis, he said.

To run power supply noise analysis, Yuan said, changes are needed in library characterization, parasitic extraction, timing analysis and dynamic analysis. Voltage-dependent timing models are needed to drive voltage-drop-dependent timing analysis.

Among the solutions proposed for IC power problems is a "policy-based approach" to power management that was outlined at the workshop by Bhanu Kapoor, technology director of RTL analysis tool provider Atrenta Inc. The policy-based scheme helps designers implement appropriate design techniques, such as clock gating, early in the design cycle.

Dynamic and leakage power solutions involve different techniques, Kapoor noted. In addition to clock gating, he said, multiple voltage domains can reduce dynamic power. The idea is to run only critical portions of the chip at high voltages.

Kapoor cited one example in which running 75 percent of a chip at 60 to 70 percent of the supply voltage reduced dynamic power nearly 50 percent. The challenge is placing the correct level shifters on signals that cross voltage domains.

To control leakage power, Kapoor said, designers can use power domains that get turned off in selected modes of operation. The challenge here is ensuring the proper isolation of signals.

"You need to address things early in the design cycle to assure adherence to the best low-power design practices," Kapoor said.

Stan Krolikoski, CEO of ChipVision Design Systems AG, argued that power analysis must move up to the system level. ChipVision provides Orinoco, which identifies power problems from SystemC input. The tool uses behavioral synthesis to create a high-level floor plan and a heat map.

"Systems architects usually don't understand implementation effects," Krolikoski said. "We need tools that provide physical implementation in a way that's architect-friendly, with sufficient accuracy to guide decisions."

Mehmet Cirit, president of Library Technologies Inc., described a way to do power simulation using Verilog. The approach employs his company's PowerTeam product, which provides extensions to the Verilog simulator that let it perform dynamic power simulation using the programming language interface.

Cirit argued that event-driven simulation provides a good way to analyze power dissipation. When an input changes state, it starts a power dissipation cycle. As a signal propagates to outputs, power dissipation stops. With a Verilog power library and language extensions, Cirit said, power can be accurately modeled.

A presentation by Jason Cong, director of the VLSI CAD lab at the University of California, Los Angeles, examined architecture and synthesis for power-efficient FPGAs. These devices are power-inefficient, he noted, with power consumption from both programmable interconnects and leakage. Cong took a look at such alternatives as dual-Vdd lookup table (LUT) design, dual-Vt LUT design and Vdd-programmable blocks, as well as new synthesis algorithms.

Intel Corp. senior principal engineer Stefan Rusu discussed such high-performance MPU design challenges as inductive noise and power management. Rusu described several leakage-reduction techniques, including sleep transistors, and said CAD tools must enable power and leakage reduction.