The SmartFusion2 product range is built on 65nm Flash technology and biased heavily towards security and defense applications.
Following the acquisition of Actel, the first new FPGA from Microsemi was launched in October 2012. The SmartFusion2 product range is built on 65nm Flash technology and biased heavily toward security and defense applications. Analog components have been replaced with crypto cores. The ARM core speed has been boosted to 166MHz alongside Ethernet, CAN, USB, and PCIe interfaces. The products does include several features new to Microsemi, such as 18x18-bit multiply-accumulate blocks for performing DSP and SerDes for high-speed (5Gbit/s) serial communications. These features have been mainstream with the company's competitors for several product generations.
The SmartFusion2 family spans the density range from 6k to 150k logic elements, defined as a four-input lookup table (LUT) together with a flip-flop. Microsemi has finally dropped the VersaTiles used on earlier products and adopted a conventional four-input LUT structure in the fabric. This might be transparent to the user, but it no doubt simplifies support through third-party tools such as Aldec and Synposys. The larger devices will compete against products like the Zynq and Cyclone V SE, ST, and SX families from Xilinx and Altera. Having the SmartFusion2 ARM cores clock at 166MHz means they run considerably slower than the 800-1,000MHz versions in competing products.
Microsemi has included hard memory controllers that support DDR transfer rates of 667Mbit/s, which make the devices broadly similar to those from Xilinx and Altera.
The refocus of the SmartFusion products on security is reflected in the inclusion of features devoted to secure applications, such as a physically unclonable function and nonvolatile memories. In addition to encryption keys, the nonvolatile memories can store data such as DSP coefficients.
Before deciding how to employ the user Flash in a design, don't forget to read the data sheet carefully. There is always an endurance limit to the number of read/write cycles with Flash. For the user Flash, this limit is between 1k and 10k cycles (depending on the retention required), while the limit for reconfiguring the FPGA fabric itself is 500 cycles. So user Flash is fine for storing data that's updated very rarely (e.g. weekly), but don't use it for storing intermediate results of DSP calculations. That's why the SRAM blocks are included.
I guess it was inevitable that Microsemi would refocus the SmartFusion products on its home ground of safety-critical applications such as industrial, defense, aviation, communications, and medical. The chip design and support burden is easier for a digital product than it is for the analog designs of the original family, though it seems a pity that Microsemi has abandoned the widening of programmable devices into the mixed-signal world.
Have you used the original SmartFusion or the new SmartFusion2 products? Please tell the rest of us about your experiences.