I think we may well be seeing the start of a completely new way to test and verify SoC and FPGA designs.
These days, we're seeing more and more products in which the circuit board plays host to a system-on-chip (SoC) device along with some memory chips and relatively few other components. As its name would suggest, an SoC typically includes one or more processor cores; some on-chip memory; a host of interface functions such as USB, Ethernet, and PCIe; and a variety of peripheral functions and hardware accelerator functions.
This part took me by surprise. I had already thought about using VTOS to test and verify PCBs that were playing host to SoCs. What I hadn't considered was using VTOS to test and verify the pre-silicon SoC design itself. But this makes total sense as soon as you think about it.
When you are verifying a PCB, at least you are playing with a physical PCB. When you are verifying a pre-silicon SoC design, all you have is the hardware description language (HDL) representation. Current HDL verification techniques include software simulation and hardware emulation. But if your verification strategy is based on booting the Linux OS and then running test programs in software, you will be waiting a very long time before you see any results.
By comparison, VTOS has such a small memory footprint that you can use a software simulator or a hardware emulator to boot VTOS and run your test suite in your SoC design. Pretty cool, eh?
And this is where the tale takes another turn. Companies like Altera and Xilinx recently introduced a new class of FPGA devices that include hard processor, interface, and peripheral function cores with traditional programmable fabric. Altera calls these devices SoC FPGAs; Xilinx calls them All Programmable SoCs. Though the details vary, these devices boast a full hard-core implementation of a dual ARM Cortex-A9 microcontroller subsystem (including floating-point engines, on-chip cache, counters, timers, etc.), coupled with a wide range of hard-core interface functions (SPI, I2C, CAN, etc.) and a hard-core dynamic memory controller. All this is augmented with a large quantity of traditional programmable fabric, a bunch of high-speed serial interfaces, and a substantial number of general-purpose input/output pins.
The hot news today is that Kozio has announced the availability of VTOS and a system-level functional test library for the Xilinx Zynq-7000 All Programmable SoC. This can be used with the Cadence Virtual System Platform or the community-based ZedBoard.
There are several great things about using this approach for verifying your FPGA-based designs. First of all, you can verify your pre-silicon version of the design using a software simulator (or in the physical FPGA) at the system level to ensure that everything functions as planned. The same repeatable test scenarios can be repeated post-silicon on the final board-level product. (In the case of an FPGA design, we do have a physical FPGA to hand. I say "pre-silicon" and "post-silicon" to relate this to the SoC design flow we discussed earlier.)
To put this another way, if this is implemented appropriately, the test suite created by the hardware designers to verify the original FPGA-based design can subsequently be delivered with the board-level product to the manufacturing group to make sure the board is built correctly. It can then be sent to the software developers. If a software application fails when accessing the main memory, for example, the developers can run the appropriate tests to verify that the memory subsystem on that development board is fully functional before devoting time to debugging the application itself. There are few things more frustrating than spending copious amounts of time attempting to debug a software issue, only to find that the problem resides in the hardware (or vice versa).
I think we may well be seeing the start of a completely new way to test and verify SoC and FPGA designs. What do you think about all this?