In this installment of our 3D IC mini-series, we ponder the use of esoteric materials and monolithic 3D IC technologies.
This is so ingenious. We take a second wafer that is also ~700 μm (0.7 mm) thick. We create its active layer using a high-temperature process combined with the usual suspects (doping agents) to create P-type and N-type silicon. As usual, this active/device layer is ~20 nm thick (1/50th of 1 μm).
This is the clever part. We use a lower-temperature process to dope the entire wafer with hydrogen to a very precise depth of ~50 nm. This does not change the characteristics of the P-type and N-type silicon in the active layer per se. However, as we shall see, it does change the character of the silicon as a whole.
Once we've doped the wafer with hydrogen, we put a protective layer of silicon dioxide on top (no metallization at this stage), leaving us with a wafer that looks something like the following.
Cross section of a second, hydrogen-doped wafer.
The next step is to flip this wafer over and lay it on top of the first wafer. Applying the correct combination of pressure and temperature creates a strong bond between the two layers of silicon dioxide (SiO2) -- so strong, in fact, that the entire assembly can now be treated as a single, thick wafer, as illustrated below.
Flipping the second wafer over and attaching it to the first.
Are you ready for the really good part? Using mechanical and thermal stress, it is possible to cleave the second wafer along the edge of the hydrogen-doped strata. This well-known semiconductor process has been used to build silicon-on-insulator wafers for the last 20 years. Remember that this layer is only ~50 nm thick (1/20th of 1 μm). Next, we pattern vias into this top layer. Unlike conventional through-silicon vias, which have a diameter on the order of 5 μm, these vias are only 1/100th that size, or ~50 nm in diameter. Finally, we lay down more layers of metallization -- anywhere from two to 10 layers, depending on what we are trying to achieve.
Cleaving the second wafer and then adding vias and metal layers.
Let's recap. Our original wafer was ~700 μm (0.7 mm) thick. All the metallization and dielectric layers we add on top of this wafer come to ~1 μm (0.001 mm), and this really is a worst-case scenario. With metallization, our wafer is now ~701 μm (0.701 mm) thick.
The cleaved portion of our second wafer, along with its metal layers, has a total thickness of ~1 μm (0.001 mm). Again, this is a worst-case scenario. The point is that we can theoretically repeat this process over and over, with each new wafer/metallization combo adding only ~1 μm (0.001 mm) to the total thickness. Finally, we could employ a back grinding process to reduce the original wafer to ~200 μm (0.2 mm) in thickness, as illustrated in the following image.
Adding multiple wafer/metallization combos to the original wafer.
Proponents of this type of 3D IC technology say its microscopic vias make it possible to make thousands of times more vertical (interlayer) connections than can be realized using conventional through-silicon vias in today's active-on-active 3D IC/SiP technologies. At the time of this writing, this type of technology is still in its infancy, but I believe it could be a real game changer in the not-so-distant future.
Last but not least, remember that this column has provided only a high-level introduction to a very, very complicated topic. If you are interested in learning more, check out the MonolithIC 3D website, and feel free to contact its president and CEO, Zvi Or-Bach, directly at firstname.lastname@example.org. (He told me I could say this.)
— Max Maxfield, Editor of All Things Fun & Interesting