The JESD204 interface was originally rolled out several years ago, but has undergone revisions that are making it a much more attractive and efficient converter interface.
In July 2011, the second and current revision of the standard, JESD204B, was released. One of the key components of the revised standard was the addition of provisions to achieve deterministic latency. In addition, the data rates supported were pushed up to 12.5 Gbit/s, broken down into different speed grades of devices. This revision of the standard calls for the transition from using the frame clock as the main clock source to using the device clock as the main clock source. The illustration below provides a high-level representation of a JESD204B system that highlights the additional capabilities added by the JESD204B revision.
High-level representation of a JESD204B system.
In the previous two versions of the JESD204 standard, there were no provisions defined to ensure deterministic latency through the interface. The JESD204B revision remedies this issue by providing a mechanism to ensure that, from power-up cycle to power-up cycle and across link re-synchronization events, the latency should be repeatable and deterministic. One way this is accomplished is by initiating the initial lane alignment sequence in the converter(s) simultaneously across all lanes at a well defined moment in time by using an input signal called SYNC~.
Another implementation is to use the SYSREF signal, which is a newly defined signal for JESD204B. The SYSREF signal acts as the master timing reference and aligns all the internal dividers from device clocks as well as the local multi-frame clocks in each transmitter and receiver. This helps to ensure deterministic latency through the system. The JESD204B specification calls out three device sub-classes: Sub-class 0 (no support for deterministic latency), Sub-class 1 (deterministic latency using SYSREF), and Sub-class 2 (deterministic latency using SYNC~). Sub-class 0 can simply be compared to a JESD204A link. Sub-class 1 is primarily intended for converters operating at or above 500 MSPS, but it can be used on converters operating below 500 MSPS to achieve greater timing resolution. Sub-class 2 is primarily for converters operating below 500 MSPS.
In addition to the deterministic latency, the JESD204B version increases the supported lane data rates to 12.5 Gbit/s and divides devices into three different speed grades. The source and load impedance is the same for all three speed grades being defined as 100Ω ±20%. The first speed grade in JESD204B aligns with the lane data rates from the JESD204 and JESD204A versions of the standard and defines the electrical interface for lane data rates up to 3.125 Gbit/s. The second speed grade defines the electrical interface for lane data rates up to 6.375 Gbit/s. This speed grade lowers the minimum differential voltage level to 400 mV peak-to-peak, down from 500 mV peak-to-peak for the first speed grade. The third speed grade defines the electrical interface for lane data rates up to 12.5 Gbit/s. This speed grade lowers the minimum differential voltage level required for the electrical interface to 360 mV peak-to-peak. As the lane data rates increase for the speed grades, the minimum required differential voltage level is reduced to make physical implementation easier by reducing required slew rates in the drivers.
To allow for more flexibility, the JESD204B revision transitions from the frame clock to the device clock. Previously, in the JESD204 and JESD204A revisions, the frame clock was the absolute timing reference in the JESD204 system. Typically, the frame clock and the sampling clock of the converter(s) were the same. This did not offer a lot of flexibility and could cause undesired complexity in system design when attempting to route this same signal to multiple devices and account for any skew between the different routing paths. In JESD204B, the device clock is the timing reference for each element in the JESD204 system. Each converter and receiver receives its respective device clock from a clock generator circuit, which is responsible for generating all device clocks from a common source. This allows for more flexibility in the system design, but requires that the relationship between the frame clock and device clock be specified for a given device.
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