One of the most useful views we found in Blue Pearl's tool is its reachability analysis. It will automatically detect FSMs and analyze them structurally. In addition to reporting on all state transitions, the tool will inform you if there are any unreachable or dead states in your state machine. A picture is worth a thousand words. Consider the following bubble diagram screen shot and the associated RTL code. Which view would you prefer for analyzing dead states in your FSM?
Graphical representation of an FSM extracted from the HDL. (Click here for a larger image.)
In addition, the run time for this type of tool is far less than a traditional simulation, and it can be used while the RTL is being developed, without requiring a testbench. It's obvious that linting tools have come a long way. We at TeamCVC are exploring this topic more, and we will address some more features of this technology in a followup article.
Srinivasan Venkataramanan is the chief technology officer at CVC Pvt Ltd, a Verilog and System Verilog training and consulting firm in Bangalore, India. His areas of interest are emerging verification solutions and methodologies such as SystemVerilog, UVM, VMM, OVM, and SoC verification using graph-based scenario models; IP verification using formal methods, and low-power design verification with UPF. He provides support to leading-edge semiconductor design companies on their verification methodologies and challenges. He holds a master's degree in VLSI design from the Indian Institute of Technology in Delhi and a bachelor's degree in electrical engineering from TCE in Madurai. He can be contacted at firstname.lastname@example.org.