Secret sauce: All about IP
Today it is hard to find an IC or SoC that doesn't incorporate a substantial amount of IP (intellectual property). To that end, designers will benefit from a tool suite that adopts industry standards and offers tools specifically to facilitate the creation, integration, and reuse of IP.
In order to build IP quickly and improve design productivity, designers should seek tools that allow them to integrate IP into their designs at the interconnect level, rather than at the pin level. With such a tool, designers can drag and drop the pieces of IP on to their design, and the tool will check up front that the respective interfaces are compatible. If they are, designers can draw one line between the cores, and the tool will automatically infer the correct interconnect logic and data movers that connect the IP.
Once a designer has merged four or five blocks into the design with an IP integrator tool feature, the designer can take the output of that process and package it to create IP subsystems that other people can leverage in future designs, thereby saving integration and verification time.
Abstraction and automation
Abstraction and automation accelerate product development, enable software developers to use custom hardware accelerators, and help systems engineers optimize hardware and software performance. Abstractions push beyond traditional RTL design methodologies to automate all aspects of system development and algorithm deployment into FPGAs, SoCs, and 3D ICs. It takes a strong alliance of strategic business partners to deliver a comprehensive set of solutions that accelerate the development process by leveraging abstractions that best fit the design team and target application.
Automation of abstractions is made possible by the adoption of industry standards and open-source communities. By working with tool suites that leverage industry standard programming languages and the Eclipse-based tool chains, the ARM AMBA AXI4 interface, and standards-based plug-and-play IP with IP-XACT and IEEE1735 encryption, design teams can easily incorporate design methodologies, tools, and IP that facilitate the automation of All Programmable FPGAs, SoCs, and 3D ICs.
C-based IP generation
High-Level Synthesis (HLS) advanced algorithms used today in wireless, medical, defense, and consumer applications are more sophisticated than ever before. To model these algorithms, many design teams turn to C/C++, OpenCL, or SystemC because of the sheer simulation performance over RTL-based simulations. In some cases, C code runs 1,000 times faster than the corresponding RTL. The challenge becomes the need to recode these algorithms in RTL for hardware implementation, which is time consuming and error prone. Design teams should look to leverage a tool suite with C-based IP generation to accelerate the process by enabling the C specification to be directly targeted into programmable devices without the need to create RTL by hand.
Tools for the next era of programmable design
EDA technology has evolved greatly over the last 15 years. It is important that today's designers seek next-generation development tools built from the ground up to address the productivity bottlenecks in system-level integration and implementation.
Leveraging a tool suite that employs the latest EDA technologies and standards, and that will scale nicely into the foreseeable future, will radically improve design productivity and quality of results, thereby allowing designers to create better systems faster and with fewer chips.
Tom Feist is senior director of Xilinx Design Methodology Marketing.