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The Most Under-rated FPGA Design Tool Ever

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traneus
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integer multiply
traneus   12/31/2015 10:15:33 PM
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When two finite-length integers (signed or unsigned) are multiplied together, the product's length is the sum of the lengths of the two factors. Do VHDL or Verilog handle multiply this way?

In my limited experience with C, the product is truncated to the length of one factor. Thus, to get the full-length product, one must first cast the two factors to double-original-length integers and then do the multiply.

Kevin Neilson
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Re: Existing HDLs Provide Similar Solutions
Kevin Neilson   9/14/2015 1:14:31 PM
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I agree.  I would prefer that all of this tool development effort would instead go into adding more SystemVerilog construct support in the synthesizer.  

traneus
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Re: Quaternion/matrix math
traneus   9/14/2015 11:25:22 AM
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xeinth, you state the tool does vector/complex math. Does the tool do quaternion or matrix math? These are useful for rotations in three dimensions.

xeinth
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Re: Existing HDLs Provide Similar Solutions
xeinth   9/13/2015 4:41:48 AM
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Cognoscan,

I understand where you are coming from, but this flow does allow you to automaticlaly pipeline a design and do vector/complex math dyanmically.  While you could probably add vector math support in some way to HDL languages, you really cannot automtically pipeline an algorithm with HDL.

Consider Arria 10 and Stratix 10, they have top speeds of roughly 500Mhz and 1Ghz respectively.  If you had a simple algorithm which runs at say 250Mhz and needs to be folded to timeshare resources, then optimally pipeline the registers in a way that works with Hyperflex, and then update the statemachines to account for the latency delays of various memories, multipliers in an automated fashion, would you really write your HDL in a way to account for all of that? 

I suppose you could claim its possible, but no one really ever does it because its too much work, and the nuances of every FPGA family end up being unique requiring some hand tuning. 

x

PS/Disclaimer:  I work for Altera, but not part of this team, just have used the tool for IP development.

elizabethsimon
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But does it work for Xilinx or Microsemi?
elizabethsimon   9/11/2015 11:19:31 AM
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The company I work for uses FPGAs from all major vendors so we have a requirement that common blocks be written to be vendor agnostic.

How well does this tool play with other pre-written blocks?

 

Gregory.Nash_#1
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Re: Existing HDLs Provide Similar Solutions
Gregory.Nash_#1   9/11/2015 10:10:31 AM
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While it's certainly true that HDL can be parameterized for different architectures, that would still require that the engineer writing that HDL be aware of all current and future architectures.

 

And it's certainly true that engineers can write their own GUIs.

 

And they can easily link them to simulations...

 

But this tool already does all that, without requiring knowledge of many FPGA families and clairvoyance into the future and doesn't require engineers to waste time reinventing tools.

 

The ability to abstact algorithm from implementation and have a transparent link to simulation is not provided by HDL.

Cognoscan
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Existing HDLs Provide Similar Solutions
Cognoscan   9/10/2015 4:25:13 PM
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VHDL-2008 and SystemVerilog introduced a number of useful expansions to their respective languages that make so-called "HLS" tools unnecessary. Modules can be parameterized to provide the same level of configuration, and can be easily chained together when using interfaces in SystemVerilog or records in VHDL. The architecture-specific optimization can be turned on through synthesis tools, or made explicit through parameters / defines. In short, there is practically nothing here that can't be replicated through good use of generic modules.

There are, I suppose, three actual benefits: simulation can be faster, you can use a graphical tool, and the modules are fully optimized. These are harder to overcome, but it's a matter of time, rather than something fundamental to the tools. Simulations can be optimized by ditching wire-accurate models, graphical tools can be written (if any FPGA Designer really wants one), and module optimization is something that, by the article's own admission, engineers are very good at.

So as a time/money tradeoff, it makes sense to use these tools upfront, but they don't have much benefit in the long term. And if someone ever releases a good set of generic modules/entities that replicate the MATLAB blocks, then this tool carries no real benefit at all.

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