In my previous blog entries, I discussed how transistors may soon be nearing a natural limit to their energy efficiency due to leakage. As transistors are pushed to smaller length scales, logic voltages inevitably decrease, due to limitations of materials. Examples of the relevant material properties include the achievable dopant density (which determines the steepness of junction gradients, and guards against punch-through), and the ability of gate stack materials to provide a high dielectric constant and/or to withstand high electric fields without breaking down or leaking excessively via quantum tunneling.
Once we run out of materials improvements that can be cost-effectively integrated into the manufacturing process, which must happen eventually, we will run out of ways to keep logic voltages from decreasing in proportion to device size. Unfortunately, voltages are almost too low already to satisfactorily block subthreshold leakage currents, except in high-threshold devices, which are also slow. Basically, small FETs also have a small on/off current ratio, which ends up limiting the achievable ratio between their logic performance and their power dissipation.
We may conclude that in the long run, the most power-efficient (and thus most commercially viable) transistors will probably not be the smallest transistors that can ever be manufactured. True, experimental FETs have been built with physical channel lengths of only a few nanometers, but their power efficiency will inevitably be lousy. Much larger FETs may end up faring better in the marketplace.
It's also interesting to note that the leakage problem can't be avoided by simply changing the channel material, such as moving to new (but IMHO, somewhat over-hyped) materials such as carbon nanotubes, since the expression for leakage current ultimately derives from fundamental statistical-mechanical considerations (e.g., the Boltzmann distribution) which are independent of materials.
However, strictly speaking, this leakage-based limit to energy efficiency applies only to small transistors. In fact, larger, slower transistors can actually process a logic signal with less total energy dissipation, in principle, so long as the charge transfer is done adiabatically, that is, in a gradual, controlled fashion. There is a style of low-power CMOS logic circuits known as adiabatic or energy-recovery circuits that attempts to do exactly this.
However, to avoid leakage by sticking with larger, slower devices implies a significant cost-efficiency and design-time overhead, in order to boost performance via greater parallelism, instead of increased clock speed. (Although it is interesting to note that major players such as Intel already seem to be diverting their architectural strategy in this direction.)
Moreover, to do extensive energy recovery (which is required, in the long run, in order to keep boosting the power-performance of an existing device technology) requires an additional clock slowdown factor, as well as reversible logic, both of which imply even greater overheads. Also, building very high-quality energy-recovering power supplies also remains a quite difficult research challenge.
In the long term, reduced manufacturing costs and a gradual migration to more parallel architectures may mean that this unfamiliar and seemingly-backwards alternative strategy of regressing to bigger, slower, but much more highly-adiabatic FETs could still win out in the long run, although if this happens, it will likely be a very gradual process, due to the steepness with which we expect the design and cost overheads of this approach to mount.
If we want to see things happen faster, I think that we need to look to new devices. That is, we need to more intensively explore alternative digital elements whose operation is based on something other than the ordinary semiconductor field effect.
One of the lesser-known (but still very interesting) alternatives to FET-based switching in electronics is a device known as the "Y-branch switch." I will review the basic principles and properties of this device, and the motivations for exploring it, in my next blog entry.
Dr. Michael P. Frank, Assistant Professor
FAMU-FSU College of Engineering
Department of Electrical & Computer Engineering
2525 Pottsdamer St, Rm 341, Tallahassee FL 32310
email@example.com, phone 850-410-6463, cell 597-2046