In addition to CPLDs, FPGAs, FPAAs, FPNAs, and programmable processors, Programmable Logic Designline is also going to cover Structured ASICs.
When I assumed editorship of this site last week, I mentioned that we weren’t going to restrict ourselves only to FPGAs and CPLDs, but instead we would also cover such topics as field-programmable processors, field-programmable analog arrays (FPAAs) and field programmable node arrays (FPNAs).
But wait, there’s more, because we are also going to cover Structured ASICs. “What! How can this be?” I hear you cry. Well, this actually makes sense on many levels. First, we have devices like HardCopy from Altera, which allow you prototype your design in a standard SRAM-based FPGA and then re-generate it as a Structured ASIC.
Next, we have companies like eASIC, who offer a unique hybrid technology that combines aspects of FPGAs with features normally associated with structured ASICs. In the case of these devices, the logical portion of the design is implemented using programmable SRAM-based look-up tables (LUTs), which are configured by means of a bit-stream loaded at power-up as in an FPGA; meanwhile, the routing is customized by means of a single via layer at the foundry.
And there’s also the fact that any design tools such as physically-aware synthesis intended for use with FPGAs and Structured ASICs share many of the same issues and solutions. But perhaps most importantly, I think that Structured ASICs are really cool, and I’m the one wearing the “I’m the Editor” T-Shirt, so after considering this issue from all sides (and from the top and the bottom), I’ve given myself permission to boldly go behind the beyond where no other Programmable Logic Designline editor has boldly gone behind, beyond, before (try saying that quickly). Until next time, have a good one!