One of the big problems with creating a standard cell ASIC is that your algorithms are largely "frozen in silicon."
One of the big problems with creating a standard cell ASIC is that your algorithms are largely "frozen in silicon." This can be a real swine in the case of markets such as wireless handheld applications, in which standards and protocols are changing on an almost daily basis. The fear is that by the time you’ve completed your masterpiece, it will no longer satisfy the requirements of "the standard du jour."
One way to get around this is to accompany the main ASIC with a smaller, cheaper, more easily modifiable component: typically a CPLD, FPGA, or Structured ASIC. In this case, the main ASIC can be used to implement the bulk of the functionality, especially the functions that are well known and unlikely to change. Meanwhile, the side chip can be used to address any changes to the original specification.
A company that specializes in this type of thing is ChipX, who have just announced their new CX6100 family of Structured ASICs featuring an integrated, silicon-proven PCI Express (PCIe) PHY core. You can read more in today's Featured Product article on PLdesignline.com.