Connecting IP cores together sounds easy if you say it quickly and wave your arms around a lot, but connecting these little scamps together is a non-trivial task.
These days, a large part of creating a new design (be it implemented as an ASIC or an FPGA) typically involves gathering a bunch of IP cores together. It all sounds so easy if you say it quickly and wave your arms around a lot, but connecting these little scamps together is a non-trivial task.
Rather than keep on re-inventing the wheel (which, by the way, is boringly round in my opinion), it makes sense to use a standard interface to link these cores together, where this interface obeys the rules of a standard socket.
This is the point where the Open Core Protocol (OCP) leaps onto the center stage, because the OCP is a common standard for IP core interfaces, or sockets, which facilitates the concept of "plug and play" design. Today's featured How To article describes how designers at eASIC used the OCP to implement a multi-port access memory with a single port SRAM for use in a digital sampling oscilloscope.