My head is spinning with all of the different reconfigurable processing technologies that are available. Of course we have FPGAs whose fabric can be configured to contain one or more soft processor cores along with hardware accelerators and general-purpose logic.
Then we have arrays of ALUs in a "sea" of programmable interconnect, such as the D-Fabrix, reconfigurable algorithm processing (RAP) technology from Elixent. Provided as IP to be incorporated into larger ASICs and ASSPs, this fabric is configured in a similar manner to an FPGA; that is, RTL is synthesized into a configuration file that is used to program the chip.
But wait, there's more, because we also have arrays of full-up processors in a "sea" of programmable interconnect, such as the picoArray offered by picoChip. Available as off-the-shelf devices, the functionality required of these little scamps is captured as a mix of VHDL and C (or assembly).
And then we have the incredibly cunning offering from Stretch Inc.. In this case, they have a chip that comprises a core processor tightly coupled with a chunk of reconfigurable fabric. They also have a tool that will analyze a C/C++ application and generate a configuration file along with a custom compiler and source-level debugger.
And there's yet more, because we mustn't neglect the board and system-level "supercomputer" implementations based on large numbers of FPGAs, such as those from Nallatech.
There's so much to keep on top of, which is why Programmable Logic DesignLine is just the place to be if you want to learn about the latest and greatest in programmable space.